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ISPLSI2032A-150LT44 Datasheet(PDF) 6 Page - Lattice Semiconductor

Part No. ISPLSI2032A-150LT44
Description  In-System Programmable High Density PLD
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Manufacturer  LATTICE [Lattice Semiconductor]
Direct Link  http://www.latticesemi.com
Logo LATTICE - Lattice Semiconductor

ISPLSI2032A-150LT44 Datasheet(HTML) 6 Page - Lattice Semiconductor

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Specifications ispLSI 2032/A
6
External Timing Parameters
Over Recommended Operating Conditions
tpd1
UNITS
-110
MIN.
TEST
COND.
1. Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-bit counter using GRP feedback.
4. Reference Switching Test Conditions section.
Table 2-0030B-110/2032
1
4
3
1
tsu2 + tco1
(
)
-80
MIN.
MAX.
MAX.
DESCRIPTION
#
2
PARAMETER
A1
Data Propagation Delay, 4PT Bypass, ORP Bypass
10.0
15.0
ns
tpd2
A2
Data Propagation Delay
ns
fmax
A3
Clock Frequency with Internal Feedback
111
84.0
MHz
fmax (Ext.)
4
Clock Frequency with External Feedback
MHz
fmax (Tog.)
5
Clock Frequency, Max. Toggle
MHz
tsu1
6
GLB Reg. Setup Time before Clock, 4 PT Bypass
ns
tco1
A7
GLB Reg. Clock to Output Delay, ORP Bypass
ns
th1
8
GLB Reg. Hold Time after Clock, 4 PT Bypass
0.0
ns
tsu2
9
GLB Reg. Setup Time before Clock
7.5
ns
tco2
10
GLB Reg. Clock to Output Delay
ns
th2
11
GLB Reg. Hold Time after Clock
0.0
ns
tr1
A12
Ext. Reset Pin to Output Delay
ns
trw1
13
Ext. Reset Pulse Duration
6.5
ns
tptoeen
B14
Input to Output Enable
ns
tptoedis
C15
Input to Output Disable
ns
tgoeen
B16
Global OE Output Enable
ns
tgoedis
C17
Global OE Output Disable
ns
twh
18
External Synchronous Clock Pulse Duration, High
4.0
ns
twl
19
External Synchronous Clock Pulse Duration, Low
4.0
ns
77.0
125
5.5
5.5
6.5
13.5
14.5
14.5
7.0
7.0
13.0
57.0
83.0
7.5
0.0
9.5
0.0
10.0
6.0
6.0
18.5
8.0
9.5
19.5
24.0
24.0
12.0
12.0


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