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LM27262 Datasheet(PDF) 4 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part No. LM27262
Description  Intel CPU Core Voltage Regulator Controller for VRD10 Compatible PCs
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Maker  NSC [National Semiconductor (TI)]
Homepage  http://www.national.com

LM27262 Datasheet(HTML) 4 Page - National Semiconductor (TI)

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Pin Description
(All pin numbers referred to here correspond to the TSSOP/
LLP package)
Pin 1/44, PHASES: tri-level logic input: HIGH logic level
switches controller into 2-phase operation mode, phases A
and C active. LOW logic level activates 3-phase operation,
phases A, B and C active, OPEN (floating) input activates
4-phase operation
Pin 2/45, IREF: connect a 1% resistor to ground to program
a precision current source for a standard offset voltage,
typically –25mV, across a resistor connected between
VPROG and VSTDOS pins. Recommended current value is
approximately 80µA. Typical resistor value is R = 1.4V /
80µA equals 17.4k.
Pin 3/46, VSTDOS: input; V
pin allows setting a programmable offset voltage (typically
25mV). The offset is programmed via an external 1% resistor
connected between the VPROG and VSTDOS pins. The
offset is the Pin 2 current multiplied by this offset program-
ming resistor.
Pin 4/47, VPROG: output used for programming a standard
offset. Connect a 1% resistor between VPROG and VST-
DOS. VPROG output voltage is the buffered internal DAC
Pin 5/48: No connect pin
Pin 6/1, SLADJ1: load line slope adjustment via external
resistor divider
Pin 7/2, SLADJ2: load line slope adjustment via external
resistor divider
Pin 8 – 13/3-8, VID0-VID5: voltage identification code inputs
Pin 14/9, VDAC: buffered output of onboard DAC. Voltage
determined by VID code.
Pin 15-18/10-13: no connect pin
Pin 19/14, CLIMADJ: output current limit adjustment input
for one phase. For 4-phase operation the current limit is 4x
the single phase current limit, for 3-phase operation it is 3x
the single phase limit, and 2x the single phase current for
2-phase operation
Pin 20/15, REFINT: internal/external voltage reference se-
lection logic input. When logic high, selects internal refer-
Pin 21/16, VCC5V: 5V power supply input to the part.
Should be decoupled to GND pin with a 1uF capacitor.
Pin 22/17, VREF: internal voltage reference output or exter-
nal voltage reference input depending on REFINT input logic
Pin 23/18, GND: the chip ground pin. Use for 5V supply
ground connection, Make a single-point ground connection
at this pin.
Pin 24 – 27/19-22: no connect pins
Pin 28-31/23-26: DRIVED-DRIVEA: PWM logic level out-
puts for phases D through A. Not short-circuit protected.
Pin 32/27, DELAY: OVP, UVP and OCP latch-off delay
adjustment pin. A delay programming capacitor is connected
between this pin and ground. This pin disables UVP, OVP
and OCP latch-off when grounded to facilitate debugging
Pin 33/28, VCORE: CPU core voltage rail connection. This
pin is the OVP/UVP sense point.
Pin 34/29, COMP: output of error amplifier. Use for external
loop compensation connection
Pin 35/30, VFB: input of error amplifier. Use for external loop
compensation connection Pin 36/31, VILD: phase D current
sense resistor low-side connection input
Pin 37/32, VIHD: phase D current sense resistor high-side
connection input
Pin 38/33, VILC: phase C current sense resistor low-side
connection input
Pin 39/34, VIHC: phase C current sense resistor high-side
connection input
Pin 40/35, VILB: phase B current sense resistor low-side
connection input
Pin 41/36, VIHB: phase B current sense resistor high-side
connection input
Pin 42/37, VILA: phase A current sense resistor low-side
connection input
Pin 43/38, VIHA: phase A current sense resistor high-side
connection input
Pin 44/39, VIDPGD: VID Power Good Delayed output. Out-
puts a VID_PWRGD signal that is delayed approximately
2msec after receiving an externally supplied active high
signal to VRON. Pin VIDPGD should be connected to the
system’s VID_PWRGD input. This delay ensures that Vcore
will power on only after the 6 VID bit signals have settled.
The LM27262 is only enabled after the delay has timed out.
Pin 45/40, VIDSLEW: connect a resistor between this pin
and the SOFTCAP pin to program VCORE slew rates for
VID transitions
Pin 46/41, SOFTCAP: soft start/soft stop capacitor connec-
tion; this output sources charging current to the softstart
capacitor at power on. An internal 50k resistor discharges
the softstart capacitor during power off
Pin 47/42, PWRGD: power good output, open drain, active
Pin 48/43, VRON: logic input that turns the switching regu-
lator on and off. If VCC5V is present when the LM27262 is
shutdown then the DRIVEx outputs are active low. VRON
has a 2msec assertion delay. When VRON is de-asserted,
the VID DAC latches the latest VID code and executes
soft-stop. There is no de-assertion delay on VRON.
LLP DAP, SUB: die substrate. The exposed die attach
should be connected to ground potentful.

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