28348-DSH-001-B
Mindspeed Technologies™
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1.0 Product Description
1.1
Overview
The CX28342/3/4/6/8 device includes two, three, four, six, and eight identical framers
that perform the following functions:
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Signal encoding and decoding
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Frame synchronization and recovery
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Alarm detection and generation
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Far End Alarm Control (FEAC) processing
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Data link processing
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Error and event counting
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Signal and frame generation
Each framer in the CX28342/CX28343/CX28344/CX28346/CX28348 device can be
configured individually and is capable of operating at 44.736 Mbps in DS3 mode and
34.368 Mbps in E3 mode. Each framer is composed of a transmitter block and a receiver
block. In addition, the CX28342/3/4/6/8 framer includes a microprocessor interface.
Data into the receiver can be in B3ZS/HDB3, AMI, or NRZ format. The B3ZS/HDB3
or AMI data is decoded and the bipolar input is converted to unipolar. The data can then
be applied to a First In First Out (FIFO) buffer to reduce jitter on the incoming data. The
FIFO buffer provides a Voltage Controlled Oscillator (VCO) control signal to an
external clock recovery circuit. A dejittered clock (RXCKI) from the VCO can then be
used to read data from the FIFO buffer going to the remaining receiver circuitry.
Each of the receiver blocks provides framing recovery for the M13/M23 DS3, C-bit
Parity DS3, E3-G.751, and E3-G.832 formatted signals. The data bits are extracted
from the received frame and transferred serially to the system. The transmitter can
process serial data from an external pin. In addition, the transmitter can generate AIS/
RAI/RDI and IDLE code. The transmitter also transmits the Link Access Direct
(LAPD) data link data in HDLC format. The HDLC data is transmitted through a 128-
byte FIFO buffer. The microprocessor can use the FIFO status for data transfer. The
transmitter can transmit the FEAC channel data in several modes.
The microprocessor interface supports the Intel and Motorola microprocessors. The
microprocessor is responsible for configuration, control, and monitoring of the
framer. The framers have various event detectors, status indicators, and counters,
which are readable by the microprocessor. The microprocessor interface includes
(depending on the device) one (CX28342/3/4) or two (CX28346/8) interrupt pins that
combine several sources of individually masked interrupts (i.e. the start and end of
events, OOF, IDLE, AIS, and RAI/RDI). Status indicators that are available to the
microprocessor through status registers are start of a Severely Errored Framing Event
(SEF), Yellow Alarm (RAI, RDI), Alarm Indication Signal (AIS), Idle, Out of Frame
(OOF), and Loss of Signal (LOS).
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