80546KF datasheet(87/138 Pages) INTEL

Part #	80546KF

Description	64-bit Intel Xeon Processor MP with up to 8MB L3 Cache

Download	138 Pages

Scroll/Zoom	100%

Manufacturer	INTEL [Intel Corporation]

Direct Link	http://www.intel.com

Logo

87 / 138 page

64-bit Intel® Xeon™ Processor MP with up to 8MB L3 Cache Datasheet

87

6

Signal Definitions

6.1

Signal Definitions

Table 6-1. Signal Definitions (Sheet 1 of 9)

Name

Type

Description

A[39:3]#

I/O

A[39:3]# (Address) define a 240-byte physical memory address space. In sub-

phase 1 of the address phase, these pins transmit the address of a transaction.

In sub-phase 2, these pins transmit transaction type information. These signals

must connect the appropriate pins of all agents on the processor front side bus.

A[39:3]# are protected by parity signals AP[1:0]#. A[39:3]# are source

synchronous signals and are latched into the receiving buffers by

ADSTB[1:0]#.

On the active-to-inactive transition of RESET#, the processors sample a subset

of the A[39:3]# pins to determine their power-on configuration. See Section 8.1.

A20M#

I

If A20M# (Address-20 Mask) is asserted, the processor masks physical

address bit 20 (A20#) before looking up a line in any internal cache and before

driving a read/write transaction on the bus. Asserting A20M# emulates the

8086 processor's address wrap-around at the 1-Mbyte boundary. Assertion of

A20M# is only supported in real mode.

A20M# is an asynchronous signal. However, to ensure recognition of this signal

following an I/O write instruction, it must be valid 6 clks before the I/O write’s

response.

ADS#

I/O

ADS# (Address Strobe) is asserted to indicate the validity of the transaction

address on the A[39:3]# and transaction request type on REQ[4:0]# pins. All

bus agents observe the ADS# activation to begin parity checking, protocol

checking, address decode, internal snoop, or deferred reply ID match

operations associated with the new transaction. This signal must connect the

appropriate pins on all processor front side bus agents.

ADSTB[1:0]#

I/O

Address strobes are used to latch A[39:3]# and REQ[4:0]# on their rising and

falling edge.

AP[1:0]#

I/O

AP[1:0]# (Address Parity) are driven by the requestor one common clock after

ADS#, A[39:3]#, REQ[4:0]# are driven. A correct parity signal is electrically high

if an even number of covered signals are electrically low and electrically low if

an odd number of covered signals are electrically low. This allows parity to be

electrically high when all the covered signals are electrically high. AP[1:0]#

should connect the appropriate pins of all processor front side bus agents. The

following table defines the coverage for these signals.

BCLK[1:0]

I

The differential bus clock pair BCLK[1:0] determines the bus frequency. All

processor front side bus agents must receive these signals to drive their

outputs and latch their inputs.

All external timing parameters are specified with respect to the rising edge of

BCLK0 crossing the falling edge of BCLK1.

Request Signals

Subphase 1

Subphase 2

A[39:24]#

AP0#

AP1#

A[23:3]#

AP1#

AP0#

REQ[4:0]#

AP1#

AP0#

Similar Part No. - 80546KF

Manufacturer	Part #	Datasheet	Description
Belden Inc.	8054	219Kb / 2P	Magnet Wire, #28 Sol BC, PUR/NYL Ins 05-05-2023
Knowles Electronics	8054	3Mb / 60P	Introduction to Knowles Precision Devices
RAF ELECTRONIC HARDWARE	8054-440-S	117Kb / 1P	ROUND INTERNAL THREAD HANDLE

More results

Similar Description - 80546KF

Manufacturer	Part #	Datasheet	Description
Intel Corporation	313079-001	3Mb / 104P	Dual-Core Intel Xeon Processor
Intel Corporation	314915-002	2Mb / 102P	Dual-Core Intel Xeon Processor
Advantech Co., Ltd.	FWA-5070	850Kb / 2P	1U Rackmount Network Appliance with Intel® Xeon® Processor Scalable Family, up to 4 NMC Slots 23-Sep-2022
Advantech Co., Ltd.	FWA-6170	1Mb / 2P	2U Rackmount Network Appliance with Intel® Xeon® Processor Scalable Family, up to 8 NMC slots 14-Dec-2017
PMC-Sierra, Inc	RM7000A	52Kb / 4P	64-Bit MIPS RISC Microprocessor with Integrated L2 Cache
	RM7065A	52Kb / 4P	64-Bit MIPS RISC Microprocessor with Integrated L2 Cache
	RM7000A-1	38Kb / 2P	64-Bit MIPS RISC Microprocessor with Integrated L2 Cache
	RM7000C	37Kb / 2P	64-Bit MIPS RISC Microprocessor with Integrated L2 Cache
DFI Inc	KH960-CM238	890Kb / 2P	Intel Xeon/7th Gen Intel CoreTM Processor COM Express Basic
Intel Corporation	243658-020	2Mb / 128P	Intel Celeron Processor up to 1.10 GHz

More results

80546KF Datasheet(PDF) 87 Page - Intel Corporation

80546KF Datasheet(HTML) 87 Page - Intel Corporation

Similar Part No. - 80546KF

Similar Description - 80546KF

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL