ICS951403YFLF-T datasheet(4/18 Pages) ICST

Part #	ICS951403YFLF-T

Description	AMD-K7 System Clock Chip

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Manufacturer	ICST [Integrated Circuit Systems]

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4 / 18 page

4

ICS951403

0486B—02/23/04

Byte 1: Output Control Register

(1= enable, 0 = disable)

Byte 2: PCI Stop Register

(1= enable, 0 = disable)

Notes:

1. Inactive means outputs are held LOW and are disabled

from switching.

2. Latched Frequency Selects (FS#) will be inverted logic

load of the input frequency select pin conditions.

Byte 4: 24/48MHz Control Register

(1= enable, 0 = disable)

T

I

B#

N

I

PD

W

PN

O

I

T

P

I

R

C

S

E

D

7-

X

d

e

v

r

e

s

e

R

6X

k

c

a

b

-

d

a

e

R

2

S

F

5X

k

c

a

b

-

d

a

e

R

1

S

F

4X

k

c

a

b

-

d

a

e

R

0

S

F

31

1

F

E

R

22

1

0

F

E

R

10

21

1

P

G

A

09

11

0

P

G

A

Byte 5: Clock Enable Control Register

(1= enable, 0 = disable)

Byte 3: CPU Free Running Control Register

(1= enable, 0 = disable)

T

I

B#

N

I

PD

W

PN

O

I

T

P

I

R

C

S

E

D

7

t

i

B7

1

F

_

K

L

C

I

C

P

6

t

i

B7

11

6

K

L

C

I

C

P

5

t

i

B6

11

5

K

L

C

I

C

P

4

t

i

B4

11

4

K

L

C

I

C

P

3

t

i

B3

11

3

K

L

C

I

C

P

2

t

i

B1

11

2

K

L

C

I

C

P

1

t

i

B0

11

1

K

L

C

I

C

P

0

t

i

B8

1

0

K

L

C

I

C

P

T

I

B#

N

I

PD

W

PN

O

I

T

P

I

R

C

S

E

D

7

t

i

B-

X

d

e

v

r

e

s

e

R

6

t

i

B-

X

d

e

v

r

e

s

e

R

5

t

i

B-

X

d

e

v

r

e

s

e

R

4

t

i

B-

X

d

e

v

r

e

s

e

R

3

t

i

B-

0

d

e

v

r

e

s

e

R

2

t

i

B-

0

C

/

T

U

P

C

1

t

i

B-

0

1

C

/

T

U

P

C

0

t

i

B-

0

2

C

/

T

U

P

C

T

I

B#

N

I

PD

W

PN

O

I

T

P

I

R

C

S

E

D

7

t

i

B4

21

8

4

/

4

2

L

E

S

z

H

M

8

4

=

1

z

H

M

4

2

=

0

6

t

i

B7

31

0

C

K

L

C

U

P

C

5

t

i

B6

31

0

T

K

L

C

U

P

C

4

t

i

B0

41

1

C

K

L

C

U

P

C

3

t

i

B9

31

1

T

K

L

C

U

P

C

2

t

i

B3

41

2

C

K

L

C

U

P

C

1

t

i

B2

41

2

T

K

L

C

U

P

C

0

t

i

B6

41

T

U

O

_

M

A

R

D

S

Byte 6: Control Register

(1= enable, 0 = disable)

Notes:

3. Bytes 7:14 not defined.

T

I

B#

N

I

PD

W

PN

O

I

T

P

I

R

C

S

E

D

7-

1

d

e

v

r

e

s

e

R

64

21

z

H

M

8

4

-

4

2

5-

1

z

H

M

8

4

4-

1

d

e

v

r

e

s

e

R

3-

1

d

e

v

r

e

s

e

R

2-

1

d

e

v

r

e

s

e

R

1-

0

t

c

e

l

e

s

y

c

n

e

u

q

e

r

f

P

G

A

z

H

M

0

.

0

5

=

1

z

H

M

6

.

6

=

0

0-

1

d

e

v

r

e

s

e

R

T

I

B#

N

I

PD

W

PN

O

I

T

P

I

R

C

S

E

D

7-

0

X

2

=

1

X

1

=

0

h

t

g

n

e

r

t

s

F

E

R

6-

0

p

o

t

s

2

:

1

T

,

2

:

1

C

U

P

C

=

0

g

n

i

n

u

r

e

r

f

2

:

1

T

,

2

:

1

C

U

P

C

=

1

5-

0

d

e

v

r

e

s

e

R

4-

X

k

c

a

b

-

d

a

e

r

#

D

A

E

R

P

S

3-

X

k

c

a

b

-

d

a

e

r

#

P

O

T

S

_

U

P

C

2-

X

k

c

a

b

-

d

a

e

r

#

P

O

T

S

_

I

C

P

1-

X

d

e

v

r

e

s

e

R

0-

0

e

l

g

o

t

d

e

p

s

P

G

A

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