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IDT74LVCH16543A Datasheet(PDF) 2 Page - Integrated Device Technology

Part No. IDT74LVCH16543A
Description  3.3V CMOS 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O, BUS-HOLD
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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IDT74LVCH16543A Datasheet(HTML) 2 Page - Integrated Device Technology

   
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INDUSTRIALTEMPERATURERANGE
2
IDT74LVCH16543A
3.3V CMOS 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS
SSOP/ TSSOP
TOP VIEW
PIN CONFIGURATION
Symbol
Description
Max
Unit
VTERM
Terminal Voltage with Respect to GND
–0.5 to +6.5
V
TSTG
Storage Temperature
–65 to +150
°C
IOUT
DC Output Current
–50 to +50
mA
IIK
Continuous Clamp Current,
–50
mA
IOK
VI < 0 or VO < 0
ICC
Continuous Current through each
±100
mA
ISS
VCC or GND
ABSOLUTE MAXIMUM RATINGS(1)
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
NOTE:
1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.
NOTE:
1. As applicable to the device type.
Symbol
Parameter(1)
Conditions
Typ.
Max.
Unit
CIN
Input Capacitance
VIN = 0V
4.5
6
pF
COUT
Output Capacitance
VOUT = 0V
6.5
8
pF
CI/O
I/O Port Capacitance
VIN = 0V
6.5
8
pF
CAPACITANCE (TA= +25°C, F = 1.0MHz)
1
OEAB
GND
1
A1
1
A2
VCC
1
A3
1
A4
GND
1
A5
1
A6
GND
VCC
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
48
49
50
51
52
53
54
55
56
1
GND
2
CEAB
25
26
27
28
32
31
30
29
1
LEAB
1
CEAB
1
A7
1
A8
2
A1
2
A2
2
A3
2
A4
2
A5
2
A6
2
A7
2
A8
2
LEAB
2
OEAB
1
OEBA
GND
1
B1
1
B2
VCC
1
B3
1
B4
GND
1
B5
1
B6
GND
VCC
GND
2
CEBA
1
LEBA
1
CEBA
1
B7
1
B8
2
B1
2
B2
2
B3
2
B4
2
B5
2
B6
2
B7
2
B8
2
LEBA
2
OEBA
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High-Impedance
2. A-to-B data flow is shown. B-to-A data flow is similar but uses xCEBA, xLEBA, and
xOEBA.
3. Before xLEAB LOW-to-HIGH transition.
Inputs
Latch Status
Output Buffers
xCEAB
xLEAB
xOEAB
xAx to xBx
xBx
H
X
X
Storing
High Z
X
X
H
Storing
High Z
L
L
L
Transparent
Current A Inputs
L
H
L
Storing
Previous
(3) A Inputs
L
L
H
Transparent
High Z
L
H
H
Storing
High Z
X
H
X
Storing
NotRecommended
FUNCTION TABLE (EACH8-BITSECTION)(1,2)
Pin Names
Description
xOEAB
A-to-B Output Enable Input (Active LOW)
xOEBA
B-to-A Output Enable Input (Active LOW)
xCEAB
A-to-B Enable Input (Active LOW)
xCEBA
B-to-A Enable Input (Active LOW)
xLEAB
A-to-B Latch Enable Input (Active LOW)
xLEBA
B-to-A Latch Enable Input (Active LOW)
xAx
A-to-B Data Inputs or B-to-A 3-State Outputs(1)
xBx
B-to-A Data Inputs or A-to-B 3-State Outputs(1)
PIN DESCRIPTION


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