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LAN7430T/Y9X Datasheet(PDF) 8 Page - Microchip Technology |
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LAN7430T/Y9X Datasheet(HTML) 8 Page - Microchip Technology |
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8 / 77 page  LAN7430/LAN7431 DS00002631D-page 8 2018-2019 Microchip Technology Inc. 2.0 INTRODUCTION 2.1 General Description The LAN7430/LAN7431 is a highly integrated PCIe to Gigabit Ethernet Controller, with IEEE Std 1588TM-2008 and advanced power management features, that provides a high performance and cost effective PCIe/Ethernet bridging solution for automotive and industrial applications. The PCIe 3.1 PHY supports 1 Lane at 2.5GT/s for chip-to-chip and card-to-card connectivity across a combination of printed circuit boards, connectors, backplane wirings, and cables. The LAN7430 has an integrated 10/100/1000 Ethernet PHY port with IEEE 802.3az Energy Efficient Ethernet (EEE) and 10BASE-Te support, while the LAN7431 supports either a RGMII (v1.3 and v2.0) or a MII MAC port for direct con- nectivity to transceivers, such as 100BASE-T1 or HDBaseT. The LAN7430/LAN7431 further integrates PCIe Endpoint Controller, DMA Controller, Receive Filtering Engine, FIFO Controller, Ethernet MAC, EEPROM Controller, OTP Memory, TAP Controller, PME, and Clock/Reset/Power Manage- ment functions. The IEEE1588-2008 PTP functions provide hardware support for the IEEE Std 1588-2008 (v2) Precision Time Protocol (PTP), allowing clock synchronization with remote Ethernet devices, packet time stamping, and time driven event gen- eration. The device may function as a master or a slave clock per the IEEE Std 1588-2008 specification. End-to-end and peer-to-peer link delay mechanisms are supported as are one-step and two-step operations. Power Management functions include: • Enabling the host to place the device in a reduced power state, by selectively disabling internal clocks, placing it into EEE Low Power Idle mode, and powering down the Ethernet PHY (LAN7430 only). • Providing for detection of various wakeup events. • Providing a host-readable READY flag which is set when the device is fully operational. • Controlling the loading of OTP or EEPROM values after a system reset. • Supporting D0 and D3hot and D3cold states • Supporting L0s, L1 states and L1.1 and L1.2 Sub-states Single 3.3V supply operation is achieved by enabling the on-chip Switching and LDO Regulators to supply the core and I/O voltages. An internal EEPROM controller exists to load PCIe and MAC Address configuration parameters. For EEPROM-less applications, the LAN7430/LAN7431 provides 1K Bytes of OTP memory that can be used to preload this same config- uration data before enumeration. The integrated IEEE 1149.1 compliant TAP controller provides boundary scan via JTAG. Device specific features that do not pertain to the entire LAN7430/LAN7431 family are called out independently through- out this document. Table 2-1 provides a summary of the feature differences between family members: TABLE 2-1: LAN7430/LAN7431 FAMILY FEATURE MATRIX LAN7430 48-SQFN X X XX XXXX LAN7431 72-SQFN X X X X X XXXX |
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