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LAN7430 Datasheet(PDF) 38 Page - Microchip Technology |
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LAN7430 Datasheet(HTML) 38 Page - Microchip Technology |
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38 / 77 page  LAN7430/LAN7431 DS00002631D-page 38 2018-2019 Microchip Technology Inc. 6.9.2 TX PATH (HOST TO ETHERNET) The 20 KB TX FIFO buffers data transferred by the DMAC from system memory. The FCT is responsible for extracting the Ethernet frames embedded in the data and passing them to the MAC. The FCT receives valid data from the DMAC and writes it into the TX FIFO. The write side of the FCT does not perform any processing on the data. No provisions for rewind on the write side are required, as the DMAC manages its own buffer RAM and performs rewinds in the event that a DMA transfer is errored. When the FCT writes the Ethernet frame into the FCT TX FIFO RAM, it prepends a DWORD in front of the TX Command Words, used for internal processing, that contains the length of the Ethernet frame. The read side of the FCT TX FIFO is responsible for extracting the Ether- net frames. 6.10 EEPROM Controller (EEP) The device may use an external EEPROM to store the default values for the PCIe controller and the MAC address. The EEPROM controller supports most “93C56 or 93C66” type 256/512 byte EEPROMs. A total of nine address bits are used. After a system-level reset occurs, the device loads the default values from EEPROM. The device is connected to the PCIe bus but responds with CRS until this process is completed. The EEPROM controller also allows the Host to read, write and erase the contents of the Serial EEPROM. 6.10.1 EEPROM AND OTP RELATIONSHIP A detected external EEPROM alway takes precedence over the OTP. When determining the source to configure the device the following order is used. 1. EEPROM Configuration 2. OTP Configuration 3. CSR defaults The Configuration and Status Registers defaults are used if neither the EEPROM nor OTP is determined to be config- ured. 6.10.2 EEPROM / OTP AUTO-LOAD Certain system level resets (PCIe Fundamental Reset, Hot Resets, Function-Level Reset (FLR), Power Management Soft Reset, Power-On Reset (POR), External Chip Reset (RESET_N) and Soft Reset) may cause the EEPROM or OTP contents to be auto-loaded into the device. Depending on the reset event, either the PCIe Configuration registers, the system Configuration Status Registers, or both are programmed. See Section 6.12, "Resets" for additional information. 6.10.2.1 Magic Byte 6.10.2.1.1 EEPROM After a reset, the EEPROM loader attempts to read the first byte of data from the EEPROM. If the value A5h or AAh is read from the first address, then the EEPROM loader will assume that a programmed external Serial EEPROM is pres- ent. A value of AAh in the first address indicates that only the MAC address is to be read and used. 6.10.2.1.2 OTP As with the EEPROM, a signature is required to define whether or not the OTP has been programmed. If the value F3h or F7h is found at byte 0, the OTP shall be determined to be programmed. Note: A Microwire-style 2K/4K EEPROM that is organized for 256/512 x 8-bit operation must be used. Note: All EEPROM configuration is to be performed via the MPLAB Connect Configurator programming tool. Refer to Section 5.2, "Programming Tools" for additional information. APPLICATION NOTE: Certain reset events cause a restoration from previously read EEPROM / OTP values rather than rereading the EEPROM or OTP. |
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