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74AC899 Datasheet(PDF) 2 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part No. 74AC899
Description  9-Bit Latchable Transceiver with Parity Generator/Checker
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Maker  NSC [National Semiconductor (TI)]
Homepage  http://www.national.com
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74AC899 Datasheet(HTML) 2 Page - National Semiconductor (TI)

 
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Pin Names
Description
A0–A7
A Bus Data InputsData Outputs
B0–B7
B Bus Data InputsData Outputs
APAR BPAR
A and B Bus Parity Inputs
ODDEVEN
ODDEVEN Parity Select Active
LOW for EVEN Parity
GBA GAB
Output Enables for A or B Bus
Active LOW
SEL
Select Pin for Feed-Through or
Generate Mode LOW for Generate
Mode
LEA LEB
Latch Enables for A and B Latches
HIGH for Transparent Mode
ERRA ERRB
Error Signals for Checking
Generated Parity with Parity In
LOW if Error Occurs
Functional Description
The ’AC’ACT899 has three principal modes of operation
which are outlined below These modes apply to both the A-
to-B and B-to-A directions
Bus A (B) communicates to Bus B (A) parity is generat-
ed and passed on to the B (A) Bus as BPAR (APAR) If
LEB (LEA) is HIGH and the Mode Select (SEL) is LOW
the parity generated from B 07
(A 07 ) can be
checked and monitored by ERRB (ERRA)
Bus A (B) communicates to Bus B (A) in a feed-through
mode if SEL is HIGH Parity is still generated and
checked as ERRA and ERRB in the feed-through mode
(can be used as an interrupt to signal a dataparity bit
error to the CPU)
Independent Latch Enables (LEA and LEB) allow other
permutations of generatingchecking (see Function Ta-
ble below)
Function Table
Inputs
Operation
GAB
GBA
SEL
LEA
LEB
H
H
X
X
X
Busses A and B are TRI-STATE
H
L
L
L
H
Generates parity from B 07 based on OE (Note 1) Generated parity
x APAR Generated parity checked against BPAR and output as
ERRB
H
L
L
H
H
Generates parity from B 07 based on OE Generated parity
x
APAR Generated parity checked against BPAR and output as ERRB
Generated parity also fed back through the A latch for generatecheck
as ERRA
H
L
L
X
L
Generates parity from B latch data based on OE Generated parity
x APAR Generated parity checked against latched BPAR and
output as ERRB
H
L
H
X
H
BPARB 07
x APARA07 Feed-through mode Generated parity
checked against BPAR and output as ERRB
H
L
H
H
H
BPARB 07
x APARA 07
Feed-through mode Generated parity checked against BPAR and
output as ERRB Generated parity also fed back through the A latch for
generatecheck as ERRA
L
H
L
H
L
Generates parity for A 07 based on OE Generated parity
x
BPAR Generated parity checked against APAR and output as ERRA
L
H
L
H
H
Generates parity from A 07 based on OE Generated parity
x
BPAR Generated parity checked against APAR and output as ERRA
Generated parity also fed back through the B latch for generatecheck
as ERRB
L
H
L
L
X
Generates parity from A latch data based on OE Generated parity
x BPAR Generated parity checked against latched APAR and
output as ERRA
L
H
H
H
L
APARA 07
x BPARB 07
Feed-through mode Generated parity checked against APAR and
output as ERRA
L
H
H
H
H
APARA 07
x BPARB 07
Feed-through mode Generated parity checked against APAR and
output as ERRA Generated parity also fed back through the B latch for
generatecheck as ERRB
H e HIGH Voltage Level
L e LOW Voltage Level
X e Immaterial
Note 1
OE e ODDEVEN
2


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