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UPD70F3116GJA-UEN Datasheet(PDF) 10 Page - NEC |
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UPD70F3116GJA-UEN Datasheet(HTML) 10 Page - NEC |
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10 / 826 page  10 User’s Manual U14492EJ5V0UD 4.3.1 Chip select control function ....................................................................................................... 102 4.4 Bus Cycle Type Control Function ......................................................................................... 105 4.5 Bus Access .............................................................................................................................. 106 4.5.1 Number of access clocks........................................................................................................... 106 4.5.2 Bus sizing function..................................................................................................................... 107 4.5.3 Word data processing format..................................................................................................... 107 4.5.4 Bus width ................................................................................................................................... 108 4.6 Wait Function........................................................................................................................... 114 4.6.1 Programmable wait function ...................................................................................................... 114 4.6.2 External wait function ................................................................................................................ 116 4.6.3 Relationship between programmable wait and external wait ..................................................... 116 4.7 Idle State Insertion Function.................................................................................................. 117 4.8 Bus Hold Function .................................................................................................................. 118 4.8.1 Function outline ......................................................................................................................... 118 4.8.2 Bus hold procedure ................................................................................................................... 118 4.8.3 Operation in power save mode.................................................................................................. 119 4.8.4 Bus hold timing .......................................................................................................................... 119 4.9 Bus Priority Order ................................................................................................................... 120 4.10 Boundary Operation Conditions............................................................................................ 120 4.10.1 Program space .......................................................................................................................... 120 4.10.2 Data space ................................................................................................................................ 120 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION .................................................................121 5.1 SRAM, External ROM, External I/O Interface........................................................................ 121 5.1.1 Features .................................................................................................................................... 121 5.1.2 SRAM, external ROM, external I/O access ............................................................................... 122 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) ....................................................................127 6.1 Features ................................................................................................................................... 127 6.2 Configuration........................................................................................................................... 128 6.3 Control Registers .................................................................................................................... 129 6.3.1 DMA source address registers 0 to 3 (DSA0 to DSA3) ............................................................. 129 6.3.2 DMA destination address registers 0 to 3 (DDA0 to DDA3) ...................................................... 131 6.3.3 DMA transfer count registers 0 to 3 (DBC0 to DBC3)................................................................ 133 6.3.4 DMA addressing control registers 0 to 3 (DADC0 to DADC3) ................................................... 134 6.3.5 DMA channel control registers 0 to 3 (DCHC0 to DCHC3)........................................................ 136 6.3.6 DMA disable status register (DDIS)........................................................................................... 138 6.3.7 DMA restart register (DRST) ..................................................................................................... 138 6.3.8 DMA trigger factor registers 0 to 3 (DTFR0 to DTFR3) ............................................................. 139 6.4 Transfer Mode.......................................................................................................................... 142 6.4.1 Single transfer mode ................................................................................................................. 142 6.4.2 Single-step transfer mode ......................................................................................................... 144 6.4.3 Block transfer mode................................................................................................................... 145 6.5 Transfer Types......................................................................................................................... 145 6.5.1 Two-cycle transfer ..................................................................................................................... 145 6.6 Transfer Target ........................................................................................................................ 146 6.6.1 Transfer type and transfer target ............................................................................................... 146 6.6.2 External bus cycles during DMA transfer (two-cycle transfer) ................................................... 147 |
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