IN24LC02B

Figure 3. Bus timing Data

FUNCTIONAL DESCRIPTION

The IN24LC02B supports a bidirectional two wire bus and data transmission protocol. A device

that sends data onto the bus is defined as transmitter, and a device receiving data as receiver. The

bus has to be controlled by a master device which generates the serial clock (SCL), controls the bus

access, and generates the START and STOP conditions, while the IN24LC02B works as slave.

Both, master and slave can operate as transmitter or receiver but the master device determines

which mode is activated.

BUS CHARACTERISTICS

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus is not busy.

• During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in

the data line while the clock line is HIGH will be interpreted as a START or STOP condition.

Accordingly, the following bus conditions have been defined (see Figure 4).

Bus not Busy (A)

Both data and clock lines remain HIGH.

Start Data Transfer (B)

A HIGH to LOW transition of the SDA line while the clock (SCL) is HIGH determines a START

condition. All commands must be preceded by a START condition.

Stop Data Transfer (C)

A LOW to HIGH transition of the SDA line while the clock (SCL) is HIGH determines a STOP

condition. All operations must be ended with a STOP condition.

Data Valid (D)

The state of the data line represents valid data when, after a START condition, the data line is stable

for the duration of the HIGH period of the clock signal.

The data on the line must be changed during the LOW period of the clock signal. There is one clock

pulse per bit of data.

Each data transfer is initiated with a START condition and terminated with a STOP condition. The

number of the data bytes transferred between the START and STOP conditions is determined by the

master device and is theoretically unlimited, although only the last sixteen will be stored when

doing a write operation. When an overwrite does occur it will replace data in a first in first out

fashion.

Acknowledge

Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of

each byte. The master device must generate an extra clock pulse which is associated with this

acknowledge bit.

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