HMS87C1X04B/08B/16B
60
SEP. 2004 Ver 1.03
The interrupts are controlled by the interrupt master enable flag
I-flag (bit 2 of PSW), the interrupt enable register (IENH, IENL)
and the interrupt request flags (in IRQH, IRQL) except Power-on
reset and software BRK interrupt.
Interrupt enable registers are shown in Figure 16-2 . These regis-
ters are composed of interrupt enable flags of each interrupt
source, these flags determines whether an interrupt will be ac-
cepted or not. When enable flag is “0”, a corresponding interrupt
source is prohibited. Note that PSW contains also a master enable
bit, I-flag, which disables all interrupts at once.
Figure 16-2 Interrupt Enable Registers and Interrupt Request Registers
When an interrupt is occurred, the I-flag is cleared and disable
any further interrupt, the return address and PSW are pushed into
the stack and the PC is vectored to. Once in the interrupt service
routine the source(s) of the interrupt can be determined by polling
the interrupt request flag bits.
The interrupt request flag bit(s) must be cleared by software be-
fore re-enabling interrupts to avoid recursive interrupts. The In-
terrupt Request flags are able to be read and written.
Reset/Interrupt
Symbol Priority Vector Addr.
Hardware Reset
External Interrupt 0
External Interrupt 1
Timer 0
Timer 1
External Interrupt 2
External Interrupt 3
Timer 2
Timer 3
A/D Converter
Watch Dog Timer
Basic Interval Timer
Serial Interface
RESET
INT0
INT1
Timer 0
Timer 1
INT2
INT3
Timer 2
Timer 3
A/D C
WDT
BIT
SPI
-
1
2
3
4
5
6
7
8
9
10
11
12
FFFEH
FFFAH
FFF8H
FFF6H
FFF4H
FFF2H
FFF0H
FFEEH
FFECH
FFEAH
FFE8H
FFE6H
FFE4H
Table 16-1 Interrupt Priority
IENH
ADDRESS : E2H
RESET VALUE : 0000_0000
INT0E
INT1E
T0E
T1E
INT2E
INT3E
T2E
T3E
Interrupt Enable Register High
IENL
ADDRESS : E3H
RESET VALUE : 0000_----
ADE
WDTE
BITE
SPIE
-
-
-
-
Interrupt Enable Register Low
IRQH
ADDRESS : E4H
RESET VALUE : 0000_0000
INT0IF
INT1IF
T0IF
T1IF
INT2IF
INT3IF
T2IF
T3IF
Interrupt Request Register High
IRQL
ADDRESS : E5H
RESET VALUE : 0000_----
ADIF
WDTIF
BITIF
SPIF
-
-
-
-
Interrupt Request Register Low
0 : Disable
1 : Enable
Enables or disables the interrupt individually
If flag is cleared, the interrupt is disabled.
0 : Not occurred
1 : Interrupt request is occurred
Shows the interrupt occurrence
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