HMS87C1X04B/08B/16B
48
SEP. 2004 Ver 1.03
the number of timer overflow occurrence.
Timer/Counter still does the above, but with the added feature
that a edge transition at external input INTx pin causes the current
value in the Timer x register (T0,T1), to be captured into registers
CDRx (CDR0, CDR1), respectively. After captured, Timer x reg-
ister is cleared and restarts by hardware.
It has three transition modes: “falling edge”, “rising edge”, “both
edge” which are selected by interrupt edge selection register
IEDS (Refer to External interrupt section). In addition, the transi-
tion at INTx pin generate an interrupt.
Note: The CDRx, TDRx and Tx are in same address. In
the capture mode, reading operation read the CDRx, not Tx
because the reading path is opened to the CDRx, and
TDRx is read while writing operation executed.
Figure 12-6 8-bit Capture Mode
÷ 1
÷ 2
÷ 8
TM0
ADDRESS : D0H
RESET VALUE : --00_0000
-
-
CAP0
T0CK2
T0CK1
T0CK0
T0CN
T0ST
TM1
ADDRESS : D2H
RESET VALUE : 0000_0000
POL
16BIT
PWME
CAP1
T1CK1
T1CK0
T1CN
T1ST
--
1
XX
XXX
X
001
XXX
X
÷ 2
÷ 4
÷ 128
÷ 512
÷ 8
÷ 32
fxin
EC0
Edge Detector
MUX
MUX
1
1
T0 (8-bit)
CDR0 (8-bit)
T0IF
CLEAR
COMPARATOR
TIMER 0
INTERRUPT
T0ST
0 : Stop
1 : Clear and Start
T0CN
T1CN
T0CK[2:0]
T1CK[1:0]
TDR0 (8-bit)
INT0IF
INT 0
INTERRUPT
INT0
T1 (8-bit)
CDR1 (8-bit)
T1IF
CLEAR
COMPARATOR
TIMER 1
INTERRUPT
TDR1 (8-bit)
INT1IF
INT 1
INTERRUPT
INT1
T0ST
0 : Stop
1 : Clear and Start
IEDS[1:0]
IEDS[3:2]
CAPTURE
CAPTURE
÷ 2048
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