HMS87C1X04B/08B/16B
66
SEP. 2004 Ver 1.03
17. WATCHDOG TIMER
The purpose of the watchdog timer is to detect the malfunction
(runaway) of program due to external noise or other causes and
return the operation to the normal condition.
The watchdog timer has two types of clock source.
The first type is an on-chip RC oscillator which does not require
any external components. This RC oscillator is separate from the
external oscillator of the Xin pin. It means that the watchdog tim-
er will run, even if the clock on the Xin pin of the device has been
stopped, for example, by entering the STOP mode.
The other type is a prescaled system clock.
The watchdog timer consists of 7-bit binary counter and the
watchdog timer data register. When the value of 7-bit binary
counter is equal to the lower 7 bits of WDTR, the interrupt re-
quest flag is generated. This can be used as WDT interrupt or re-
set the CPU in accordance with the bit WDTON.
Note: Because the watchdog timer counter is enabled af-
ter clearing Basic Interval Timer, after the bit WDTON set to
“1”, maximum error of timer is depend on prescaler ratio of
Basic Interval Timer.
The 7-bit binary counter is cleared by setting WDTCL(bit7 of
WDTR) and the WDTCL is cleared automatically after 1 ma-
chine cycle.
The RC oscillated watchdog timer is activated by setting the bit
RCWDT as shown below.
The RC oscillation period is vary with temperature, VDD and
process variations from part to part (approximately, 40~120uS).
The following equation shows the RC oscillated watchdog timer
time-out.
TRCWDT=CLKRC×28×[WDTR.6~0]+(CLKRC×28)/2
where, CLKRC = 40~120uS
In addition, this watchdog timer can be used as a simple 7-bit tim-
er by interrupt WDTIF. The interval of watchdog timer interrupt
is decided by Basic Interval Timer. Interval equation is as below.
TWDT = [WDTR.6~0] × Interval of BIT
Figure 17-1 Block Diagram of Watchdog Timer
:
LDM
CKCTLR,#3FH; enable the RC-osc WDT
LDM
WDTR,#0FFH; set the WDT period
STOP
; enter the STOP mode
NOP
NOP
; RC-osc WDT running
:
÷ 8
÷ 16
÷ 128
÷ 256
÷ 512
÷ 1024
÷ 32
÷ 64
0
1
MUX
8
3
fxin
BITR (8-bit)
BTS[2:0]
RCWDT
Internal RC OSC
Basic Interval Timer
Interrupt
BTCL
Clear
Watchdog Timer
BITIF
7-bit Counter
WDTR (8-bit)
OFD
WDTCL
WDTON
Interrupt Request
CPU RESET
1
0
Clock Control Register
CKCTLR
ADDRESS : ECH
RESET VALUE : -001_0111
-
WAKEUP RCWDT
WDTON
BTCL
BTS2
BTS1
BTS0
-
0X
1
XXX
X
Watchdog Timer Register
WDTR
ADDRESS : EDH
RESET VALUE : 0111_1111
WDTCL
7-bit Watchdog Counter Register
Overflow Detection
Bit Manipulation Not Available
Bit Manipulation Not Available
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