HMS87C1X04B/08B/16B
SEP. 2004 Ver 1.03
43
11. Basic Interval Timer
The HMS87C1X04B/08B/16B has one 8-bit Basic Interval Tim-
er that is free-run, can not stop. Block diagram is shown in Figure
11-1 .The 8-bit Basic interval timer register (BITR) is increased
every internal count pulse which is divided by prescaler. Since
prescaler has divided ratio by 8 to 1024, the count rate is 1/8 to 1/
1024 of the oscillator frequency. As the count overflows from
FFH to 00H, this overflow causes to generate the Basic interval
timer interrupt. The BITIF is interrupt request flag of Basic inter-
val timer.
When write “1” to bit BTCL of CKCTLR, BITR register is
cleared to “0” and restart to count-up. The bit BTCL becomes “0”
after one machine cycle by hardware.
If the STOP instruction executed after writing “1” to bit WAKE-
UP of CKCTLR, it goes into the wake-up timer mode. In this
mode, all of the block is halted except the oscillator, prescaler
(only fxin
÷2048) and Timer0.
If the STOP instruction executed after writing “1” to bit RCWDT
of CKCTLR, it goes into the internal RC oscillated watchdog tim-
er mode. In this mode, all of the block is halted except the internal
RC oscillator, Basic Interval Timer and Watchdog Timer. More
detail informations are explained in Power Saving Function. The
bit WDTON decides Watchdog Timer or the normal 7-bit timer
Note: All control bits of Basic interval timer are in CKCTLR
register which is located at same address of BITR (address
ECH). Address ECH is read as BITR, written to CKCTLR.
Therefore, the CKCTLR can not be accessed by bit manip-
ulation instruction.
.
Figure 11-1 Block Diagram of Basic Interval Timer
Figure 11-2 CKCTLR: Clock Control Register
÷ 8
÷ 16
÷ 128
÷ 256
÷ 512
÷ 1024
÷ 32
÷ 64
0
1
MUX
8
3
fxin
BITR (8BIT)
BITIF
BTS[2:0]
RCWDT
Internal RC OSC
Basic Interval Timer
Interrupt
BTCL
Clear
To Watchdog Timer
Clock Control Register
CKCTLR
ADDRESS : ECH
RESET VALUE : -001_0111
-
WAKEUP RCWDT
WDTON
BTCL
BTS2
BTS1
BTS0
Basic Interval Timer Clock Selection
000 : fxin
÷ 8
001 : fxin
÷ 16
100 : fxin
÷ 128
101 : fxin
÷ 256
110 : fxin
÷ 512
111 : fxin
÷ 1024
010 : fxin
÷ 32
011 : fxin
÷ 64
Symbol
Function Description
WAKEUP
1 : Enables Wake-up Timer
0 : Disables Wake-up Timer
RCWDT
1 : Enables Internal RC Watchdog Timer
0 : Disables Internal RC Watchdog Time
WDTON
1 : Enables Watchdog Timer
0 : Operates as a 7-bit Timer
BTCL
1 : BITR is cleared and BTCL becomes “0” automatically
after one machine cycle, and BITR continue to count-up
Bit Manipulation Not Available
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