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CM1209-08MS Datasheet(PDF) 6 Page - California Micro Devices Corp

Part # CM1209-08MS
Description  4,6 & 8 Channel ESD Protection Arrays with Zener Supply Clamp
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Manufacturer  CALMIRCO [California Micro Devices Corp]
Direct Link  http://www.calmicro.com
Logo CALMIRCO - California Micro Devices Corp

CM1209-08MS Datasheet(HTML) 6 Page - California Micro Devices Corp

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© 2004 California Micro Devices Corp. All rights reserved.
6
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
L Tel: 408.263.3214
L Fax: 408.263.7846 L www.calmicro.com
01/09/04
CM1209
Application Information
Design Considerations
In order to realize the maximum protection against
ESD pulses, care must be taken in the PCB layout to
minimize parasitic series inductances on the Supply/
Ground rails as well as the signal trace segment
between the signal input (typically a connector) and the
ESD protection device. Refer to Figure 4, which illus-
trates an example of a positive ESD pulse striking an
input channel. The parasitic series inductance back to
the power supply is represented by L1 and L2. The volt-
age VCL on the line being protected is:
VCL = Fwd voltage drop of D1 + VSUPPLY + L1 x d(IESD ) / dt
+ L2 x d(IESD ) / dt
where IESD is the ESD current pulse, and VSUPPLY is
the positive supply voltage.
An ESD current pulse can rise from zero to its peak
value in a very short time. As an example, a level 4
contact discharge per the IEC61000-4-2 standard
results in a current pulse that rises from zero to 30
Amps in 1ns. Here d(IESD)/dt can be approximated by
∆IESD/∆t, or 30/(1x10-9). So just 10nH of series induc-
tance (L1 and L2 combined) will lead to a 300V incre-
ment in VCL!
Similarly for negative ESD pulses, parasitic series
inductance from the VN pin to the ground rail will lead
to drastically increased negative voltage on the line
being protected.
The CM1209 has an integrated Zener diode between
VP and VN. This greatly reduces the effect of supply rail
inductance L2 on VCL by clamping VP at the breakdown
voltage of the Zener diode. However, for the lowest
possible VCL, especially when VP is biased at a voltage
significantly below the Zener breakdown voltage, it is
recommended that a 0.22
µF ceramic chip capacitor be
connected between VP and the ground plane.
As a general rule, the ESD Protection Array should be
located as close as possible to the point of entry of
expected electrostatic discharges. The power supply
bypass capacitor mentioned above should be as close
to the VP pin of the Protection Array as possible, with
minimum PCB trace lengths to the power supply,
ground planes and between the signal input and the
ESD device to minimize stray series inductance.
Additional Information
See California Micro Devices Application Note AP209,
“Design Considerations for ESD Protection", under
Applications at www.calmicro.com.
Figure 4. Application of Positive ESD Pulse between Input Channel and Ground
N
L 2
L1
VP
V
PATH OF ESD CURRENT PULSE I
ONE
CHANNEL
OF
CM1209
CHANNEL
INPUT
GROUND RAIL
CHASSIS GROUND
POSITIVE SUPPLY RAIL
SYSTEM OR
CIRCUITRY
BEING
PROTECTED
LINE BEING
PROTECTED
ESD
0.22µF
D1
2
D
0A
20A
VCL


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