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SY87721L Datasheet(PDF) 4 Page - Micrel Semiconductor

Part No. SY87721L
Description  3.3V 28Mbps-2.7Gbps ANYRATE CLOCK AND DATA RECOVERY WITH INTEGRATED CLOCK MULTIPLIER UNIT
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Maker  MICREL [Micrel Semiconductor]
Homepage  http://www.micrel.com
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SY87721L Datasheet(HTML) 4 Page - Micrel Semiconductor

 
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SY87721L
4
Micrel, Inc.
M9999-072705
hbwhelp@micrel.com or (408) 955-1690
normally by the Receive PLL. When this input is LOW, the
data on the RDOUT output will be internally forced to a
constant LOW, the Link Fault Indicator output LFIN forced
LOW, and the clock recovery PLL forced to lock onto the
synthesized clock frequency generated from REFCLK.
VCOSEL1, VCOSEL2 [VCO Select] – TTL Inputs
These inputs select the output clock frequency range via
either one of three PLLs, or a SONET/SDH specific PLL.
Only the selected PLL is enabled. All other PLLs are
disabled. Refer to Table 3 for more details.
FREQSEL1, ..., FREQSEL3 [Frequency Select] – TTL Inputs
These inputs select the post divide ratio of the VCO.
Refer to Table 3 for more details.
DIVSEL1, ..., DIVSEL3 [Divider Select] – TTL Inputs
These inputs select the ratio between the output clock
frequency (RCLK/TCLK) and the REFCLK input frequency
as shown in Table 4. Please note that the divide by 32
selection, “011”, is only available for use when FREQSEL
are set to “000.”
REFCLK
DIVSEL1
DIVSEL2
DIVSEL3
Multiplier
00
0
1
00
1
2
01
0
4
01
1
32
10
0
8
10
1
10
11
0
16
11
1
20
Table 2(1). Reference Clock Multiplier Truth Table
Note:
1. Some combinations of FREQSEL and DIVSEL result in undefined behavior.
Refer to Table 3 for more details.
PIN NAMES
INPUTS
BRDMX [BRD Mux] – PECL Input
This signal indicates what data appears at the BRD
±
output. When logic HIGH, BRD
± is a direct copy of what
appears at RDOUTC
±. When logic low, BRD± is a copy of
what appears at RDIN
±. Unlike RDOUTC±, BRD± conveys
valid data even when ENPECL is logic LOW. Please refer
to Table 1.
BRDMX (Input)
BRD
± (Output)
0
RDIN
±
1
RDOUTC
±
Table 1. BRDMX Truth Table
RDIN
± [Serial Data Input] – Differential PECL Input
This differential input accepts the receive serial data
stream. An internal receive PLL recovers the embedded
clock (RCLK) and data (RDOUT) information. The incoming
data rate can be within one of ten frequency ranges, or can
be one of five specific frequencies, depending on the state
of the FREQSEL and VCOSEL pins. The RDIN– pin has an
internal 75K
Ω resistor tied to V
CC.
REFCLK
± [Reference Clock] – Differential PECL Input
This input is used as the reference for the internal
frequency synthesizer and the “training” frequency for the
receiver PLL to keep it centered in the absence of data
coming in on the RDIN input. The input frequency to
REFCLK is limited to 340MHz or less, depending on the
setting on the DIVSEL signals. The REFCLK– pin has an
internal 75K
Ω resistor tied to V
CC.
CD [Carrier Detect] – PECL Input
This input controls the recovery function of the Receive
PLL and can be driven by the carrier detect output of optical
modules or from external transition detection circuitry. When
this input is HIGH, the input data stream (RDIN) is recovered
VCOSEL1
PLLRN+
PLLRN—
NC
PLLRW+
PLLRW—
NC
VCCA
GNDA
PLLSW—
PLLSW+
NC
PLLSN—
PLLSN+
NC
NC
GND
ENPECL
RDOUTE+
RDOUTE—
RDOUTC+
RDOUTC—
VCCO
RCLKE+
RCLKE—
RCLKC+
RCLKC—
VCCO
TCLKE+
TCLKE—
TCLKC+
TCLKC—
64
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64-Pin
EPAD-TQFP
PACKAGE/ORDERING INFORMATION
Ordering Information(1)
Package
Operating
Package
Lead
Part Number
Type
Range
Marking
Finish
SY87721LHI
H64-1
Industrial
SY87721LHI
Sn-Pb
SY87721LHITR(2)
H32-1
Industrial
SY87721LHI
Sn-Pb
SY87721LHG(3)
H32-1
Industrial
SY87721LHG with
Pb-Free
Pb-Free bar-line indicator
NiPdAu
SY87721LHG(2, 3)
H32-1
Industrial
SY87721LHG with
Pb-Free
Pb-Free bar-line indicator
NiPdAu
Notes:
1. Contact factory for die availability. Dice are guaranteed at T
A = 25°C, DC electricals only.
2. Tape and Reel.
3. Recommended for new designs.


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