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SY87721L Datasheet(PDF) 6 Page - Micrel Semiconductor

Part No. SY87721L
Description  3.3V 28Mbps-2.7Gbps ANYRATE CLOCK AND DATA RECOVERY WITH INTEGRATED CLOCK MULTIPLIER UNIT
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Maker  MICREL [Micrel Semiconductor]
Homepage  http://www.micrel.com
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SY87721L Datasheet(HTML) 6 Page - Micrel Semiconductor

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SY87721L
6
Micrel, Inc.
M9999-072705
hbwhelp@micrel.com or (408) 955-1690
DESCRIPTION
General
The SY87721L is a complete clock and data recovery
circuit, capable of handling NRZ data rates from 28MHz
through to 2.7GHz. A reference PLL is used as a frequency
synthesizer, both to multiply a reference clock to the desired
transmit rate, and to train the recovery PLL in preparation
for actual data recovery.
Link Fault Algorithm
The SY87721L includes a Link Fault Detection circuit.
This circuit provides the following functions: Under Loss-of-
Lock (LOL) conditions, which can occur when the Carrier
Detect (CD) input is active HIGH, the output of the RCLK
approximates the output of the TCLK, within a lock range
as specified by the state of ALRSEL.
Under Loss-of-Signal (LOS) conditions, enabled by driving
the Carrier Detect (CD) input to inactive logic LOW, the
output of the RCLK becomes an exact copy of the TCLK
output. This is the result of forcing the recovery PLL to lock
to the synthesized reference.
Under LOL and LOS conditions, the LFIN output is an
inactive logic LOW.
SY87721L follows a prescribed procedure, to acquire and
recover the clock of the incoming data stream. This
procedure is triggered either by a falling edge on CD, or by
the recovered clock PLL indicating a frequency error,
compared to the synthesized reference, of greater than
500ppm or 4,500ppm, as selected by ALRSEL. With the
CD input set active HIGH, the algorithm begins by phase
and frequency training the recovery PLL to the synthesized
reference. Once the recovery PLL is within the specified
lock range, determined by the state of ALRSEL, the
SY87721L will switch from a phase-frequency comparison
with the synthesized reference, to a phase-only comparison
with the incoming data stream. When the recovery PLL is
locked to this incoming data stream (that is, after phase
step recovery), then data recovery may proceed and LFIN
asserts. Once locked and accepting data, the LFIN signal
may de-assert should the data input frequency deviate too
far from the synthesized reference frequency.
VCO Selection
SY87721L sports four complete VCO circuits. Depending
on the application and the frequency range, any one of
these four perform data recovery.
As indicated by the VCO selection table, there are three
general purpose VCOs each covering one of three frequency
ranges. However, to extend the range of the device, the
output of the VCO may be divided down.
In the case of the two highest frequency general purpose
VCOs (VCOSEL = 1, 0 or 0,1 ), this divisor is always set to
1. For the lowest frequency VCO, the FREQSEL pins select
which divisor, and hence, which range of frequencies the
VCO will work over.
In addition, for SONET/SDH applications, there is a
narrow band, extremely low jitter PLL. It also uses the
FREQSEL divisor to choose the correct SONET/SDH
frequency.
The valid modes of operation are shown in Table 3.
Notes:
1. REFCLK multiplier of 1 or 2 is not allowed in this range.
2. REFCLK multiplier of 1 is not allowed in this range.
3. Combinations of VCOSEL and FREQSEL other then those in this table result in undefined behavior, and should not be used.
VCOSEL1
VCOSEL2
FREQSEL1
FREQSEL2
FREQSEL3
Range (MHz)
00000
2488 (OC48)–2700
00001
1244-1350
00010
622 (OC12)–675
00100
311–337
00110
155 (OC3)–168
01000
1800–2700
10000
1250–1800
11000
650–1300(1)
11001
325–650(2)
11010
163–325
11011
109–216
11100
82–162
11101
55–108
11110
41–81
11111
28–54
Table 3 (3). Frequency Range Selection Truth Table


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