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SY87721L Datasheet(PDF) 5 Page - Micrel Semiconductor

Part No. SY87721L
Description  3.3V 28Mbps-2.7Gbps ANYRATE CLOCK AND DATA RECOVERY WITH INTEGRATED CLOCK MULTIPLIER UNIT
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Maker  MICREL [Micrel Semiconductor]
Homepage  http://www.micrel.com
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SY87721L Datasheet(HTML) 5 Page - Micrel Semiconductor

 
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SY87721L
5
Micrel, Inc.
M9999-072705
hbwhelp@micrel.com or (408) 955-1690
CLKSEL [Clock Select] – TTL Input
This input is used to select either the recovered clock of
the receiver PLL (CLKSEL = HIGH) or the clock of the
frequency synthesizer (CLKSEL = LOW) to the TCLK
outputs. Do not use for skew matching.
ENPECL [Enable ECL] – TTL Input
This input, when HIGH (ENPECL = 1), enables the
differential PECL outputs TCLKE
±, RDOUTE±, and RCLKE±.
It also disables the CML outputs, by setting TCLKC+,
RDOUTC+, and RCLKC+ logic HIGH and setting TCLKC–,
RDOUTC–, and RCLKC– logic LOW.
When set LOW (ENPECL = 0), this signal enables the
differential CML outputs TCLKC
±, RDOUTC±, and RCLKC±.
It also disables the PECL outputs by setting TCLKE+,
RDOUTE+, and RCLKE+ logic HIGH and setting TCLKE–,
RDOUTE– and RCLKE– logic LOW.
ALRSEL [Auto Lock Range Select] – TTL Input
This pin defines the frequency difference, and the
frequency difference hysteresis at which ‘in-lock’ and ‘out of
lock’ conditions are declared. Please refer to the “AC
Characteristics” for more details.
OUTPUTS
BRD
± [Buffered Recovered Data] – Differential CML Output
The signal is either a buffered RDIN
± or RDOUTC±,
depending on the state of the BRDMX input. This allows a
user to selectively bypass the CDR or not, as warranted by
architecture. This CML output has a voltage swing of 400mV
loaded.
LFIN [Link Fault Indicate] – O.C. TTL Output
This output indicates the status of the input data stream
RDIN. Active HIGH indicates that the internal clock recovery
PLL has locked onto the incoming data stream. LFIN will go
HIGH if CD is HIGH and RDIN is within the frequency range
of the Receive PLL (as per ALRSEL). LFIN is an
asynchronous output.
RDOUTE
± [Receive Data Out] – Differential PECL Output
These ECL 100K outputs (+3.3V referenced) represent
the recovered data from the input data stream (RDIN). It is
specified on the rising edge of RCLK.
RDOUTC
± [Receive Data Out] – Differential CML Output
This is the CML version of RDOUTE
±.
RCLKE
± [Receive Clock Out] – Differential PECL Output
These ECL 100K outputs (+3.3V referenced) represent
the recovered clock used to sample the recovered data
(RDOUT).
RCLKC
± [Receive Clock Out] – Differential CML Output
This is the CML version of RCLKE
±.
TCLKE
± [Transmit Clock Out] – Differential PECL Output
These ECL 100K outputs (+3.3V referenced) represent
either the recovered clock (CLKSEL = HIGH) used to sample
the recovered data (RDOUT) or the transmit clock of the
frequency synthesizer (CLKSEL = LOW).
TCLKC
± [Transmit Clock Out] – Differential CML Output
This is the CML version of TCLKE
±.
PLLSN+, PLLSN– [Clock Synthesis Loop Filter]
External loop filter pins for the clock synthesis narrow
band PLL.
PLLSW+, PLLSW– [Clock Synthesis Loop Filter]
External loop filter pins for the clock synthesis wide band
PLL.
PLLRN+, PLLRN– [Clock Recovery Loop Filter]
External loop filter pins for the clock recovery narrow
band PLL.
PLLRW+, PLLRW– [Clock Recovery Loop Filter]
External loop filter pins for the clock recovery wide band
PLL.
OTHERS
VCC
Supply Voltage
VCCO
Output Supply Voltage
VCCA
Analog Supply Voltage
GND
Ground
GNDA
Analog Ground
NC
These pins are for factory test, and are to be
left unconnected during normal use.


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