6
S24VP04
2008 1.4 5/15/98
FIGURE 8. CURRENT ADDRESS BYTE READ MODE
FIGURE 7. ACKNOWLEDGE POLLING
Acknowledge Polling
When the S24VP04 is performing an internal WRITE
operation, it will ignore any new START conditions. Since
the device will only return an acknowledge after it accepts
the START, the part can be continuously queried until an
acknowledge is issued, indicating that the internal WRITE
cycle is complete.
To poll the device, give it a START condition, followed by
a slave address for a WRITE operation (See Figure 7).
READ OPERATIONS
Read operations are initiated with the R/W bit of the
identification field set to “1.” There are four different read
options:
1.
Current Address Byte Read
2.
Random Address Byte Read
3.
Current Address Sequential Read
4.
Random Address Sequential Read
Current Address Byte Read
The S24VP04 contains an internal address counter which
maintains the address of the last word accessed,
incremented by one. If the last address accessed (either
a read or write) was to address location n, the next read
operation would access data from address location n+1
and increment the current address pointer. When the
S24VP04 receives the slave address field with the R/W bit
set to “1,” it issues an acknowledge and transmits the
8-bit word stored at address location n+1.
The current address byte read operation only accesses
a single byte of data. The master does not acknowledge
the transfer, but does generate a stop condition. At this
point, the S24VP04 discontinues data transmission. See
Figure 8 for the address acknowledge and data transfer
sequence.
Issue Start
Internal WRITE Cycle
In Progress;
Begin ACK Polling
Issue Slave
Address and
R/W = 0
ACK
Returned?
Next
operation a
WRITE?
Issue Byte
Address
Proceed with
WRITE
Issue Stop
Await Next
Command
Issue Stop
No
No
Yes (Internal WRITE Cycle is completed)
Yes
2008 ILL9 1.0
S
T
A
R
T
S
T
O
P
Slave Address
Device
Type
Address
Read/Write
1= Read
A2,A1,BS
SDA Bus Activity
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Master sends Read
request to Slave
Slave sends
Data to Master
Master Transmitter
to
Slave Receiver
Slave Transmitter
to
Master Receiver
1
1
1
00
1
Lack of ACK (low)
from Master
determines last
data byte to be read
1
Shading Denotes
24VP04
SDA Output Active
A
1
A
2
R
W
A
C
K
B
S
Data Byte
2008 ILL 10 1.0
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