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UPD784938 Datasheet(PDF) 31 Page - NEC

Part # UPD784938
Description  16-Bit Single-Chip Microcontrollers
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Manufacturer  NEC [NEC]
Direct Link  http://www.nec.com/
Logo NEC - NEC

UPD784938 Datasheet(HTML) 31 Page - NEC

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31
Preliminary User’s Manual U13987EJ1V0UM00
18-6
Asynchronous Serial Interface Transmission Completion Interrupt Timing ..............................................
437
18-7
Asynchronous Serial Interface Reception Completion Interrupt Timing ....................................................
438
18-8
Receive Error Timing ...................................................................................................................................
439
18-9
Example of 3-Wire Serial I/O System Configuration ..................................................................................
440
18-10
3-Wire Serial I/O Mode Block Diagram .......................................................................................................
441
18-11
Format of Clocked Serial Interface Mode Register 1 (CSIM1) and
Clocked Serial Interface Mode Register 2 (CSIM2) ...................................................................................
443
18-12
3-Wire Serial I/O Mode Timing ....................................................................................................................
444
18-13
Example of Connection to 2-Wire Serial I/O ..............................................................................................
445
18-14
Baud Rate Generator Block Diagram .........................................................................................................
449
18-15
Format of Baud Rate Generator Control Register (BRGC) and
Baud Rate Generator Control Register 2 (BRGC2) ...................................................................................
451
19-1
Clocked Serial Interface Block Diagram .....................................................................................................
458
19-2
Format of Clocked Serial Interface Mode Register (CSIM) and
Clocked Serial Interface Mode Register 3 (CSIM3) ...................................................................................
459
19-3
Example of 3-Wire Serial I/O System Configuration ..................................................................................
461
19-4
3-Wire Serial I/O Mode Timing ....................................................................................................................
462
19-5
Operation when Reception is Disabled .......................................................................................................
464
20-1
IEBus Transmission Signal Format .............................................................................................................
469
20-2
Master Address Field ...................................................................................................................................
470
20-3
Slave Address Field .....................................................................................................................................
471
20-4
Control Field .................................................................................................................................................
473
20-5
Telegraph Length Field ................................................................................................................................
473
20-6
Data Field .....................................................................................................................................................
474
20-7
Bit Configuration of Slave Status ................................................................................................................
477
20-8
Configuration of Lock Address ....................................................................................................................
478
20-9
Bit Format of IEBus .....................................................................................................................................
479
20-10
IEBus Controller Block Diagram ..................................................................................................................
481
20-11
Bus Control Register (BCR) Format ...........................................................................................................
484
20-12
Unit Address Register (UAR) Format ..........................................................................................................
486
20-13
Slave Address Register (SAR) Format .......................................................................................................
486
20-14
Partner Address Register (PAR) Format .....................................................................................................
486
20-15
Control Data Register (CDR) Format ..........................................................................................................
487
20-16
Interrupt Generation Timing (in case of <1>, <3>, <4>) ............................................................................
488
20-17
Interrupt Generation Timing (in case of <2>, <5>) .....................................................................................
488
20-18
INTIE2 Interrupt Generation Timing in Locked Status (in case of <4>, <5>) ...........................................
489
20-19
INTIE2 Interrupt Generation Timing in Locked Status (in case of <3>) ....................................................
489
20-20
Telegraph Length Register (DLR) Format ..................................................................................................
490
20-21
Data Register (DR) Format .........................................................................................................................
491
LIST OF FIGURES (9/12)
Figure No.
Title
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