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IDT72V36103L15PF Datasheet(PDF) 3 Page - Integrated Device Technology |
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IDT72V36103L15PF Datasheet(HTML) 3 Page - Integrated Device Technology |
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3 / 30 page  3 COMMERCIALTEMPERATURERANGE IDT72V3683/72V3693/72V36103 3.3V CMOS SyncFIFOTM WITH BUS-MATCHING 16,384 x 36, 32,768 x 36 and 65,536 x 36 coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchro- nous control. Communication between each port may bypass the FIFO via two mailbox registers. The mailbox registers' width matches the selected Port B bus width. Each mailbox register has a flag ( MBF1 and MBF2) to signal when new mail has been stored. Two kinds of reset are available on these FIFOs: Reset and Partial Reset. Resetinitializesthereadandwritepointerstothefirstlocationofthememoryarray and selects serial flag programming, parallel flag programming, or one of five possible default flag offset settings, 8, 16, 64, 256 or 1,024. Partial Reset also sets the read and write pointers to the first location of the memory. Unlike Reset, any settings existing prior to Partial Reset (i.e., programmingmethodandpartialflagdefaultoffsets)areretained. PartialReset is useful since it permits flushing of the FIFO memory without changing any configurationsettings. TheFIFOhasRetransmitcapability,aRetransmitisperformedafterfourclock cycles of CLKA and CLKB, by taking the Retransmit pin, RT LOW while the Retransmit Mode pin, RTMisHIGH.WhenaRetransmitisperformedtheread pointer is reset to the first memory location. These devices have two modes of operation: In the IDT Standard mode, the first word written to an empty FIFO is deposited into the memory array. A read operation is required to access that word (along with all other words residing in memory). In theFirstWordFallThroughmode(FWFT), the first word written to an empty FIFO appears automatically on the outputs, no read operation required (Nevertheless, accessing subsequent words does necessitate a formal read request). The state of the BE/ FWFTpinduringResetdetermines the mode in use. The FIFO has a combined Empty/Output Ready Flag ( EF/OR ) and a combinedFull/InputReadyFlag( FF/IR). TheEFandFFfunctionsareselected in the IDT Standard mode. EF indicates whether or not the FIFO memory is empty. FF shows whether the memory is full or not. The IR and OR functions are selected in the First Word Fall Through mode. IR indicates whether or not the FIFO has available memory locations. OR shows whether the FIFO has data available for reading or not. It marks the presence of valid data on the outputs. TheFIFOhasaprogrammableAlmost-Emptyflag( AE)andaprogrammable Almost-Full flag ( AF). AE indicateswhenaselectednumberofwordsremain intheFIFOmemory. AFindicateswhentheFIFOcontainsmorethanaselected number of words. FF/IRandAFaretwo-stagesynchronizedtotheportclockthatwritesdata into its array. EF/ORandAEaretwo-stagesynchronizedtotheportclockthat reads data from its array. Programmable offsets for AE andAF areloaded in parallel using Port A or in serial via the SD input. Five default offset settings are also provided. The AEthresholdcanbesetat8,16, 64,256or1,024locations from the empty boundary and the AF threshold can be set at 8, 16, 64, 256 or 1,024 locations from the full boundary. All these choices are made using the FS0, FS1 and FS2 inputs during Reset. Interspersed Parity is available and can be selected during a Master Reset oftheFIFO.IfInterspersedParityisselectedthenduringparallelprogramming of the flag offset values, the device will ignore data line A8. If Non-Interspersed Parity is selected then data line A8 will become a valid bit. Two or more devices may be used in parallel to create wider data paths. In First Word Fall Through mode, more than one device may be connected in series to create greater word depths. The addition of external components is unnecessary. If, at any time, the FIFO is not actively performing a function, the chip will automatically power down. During the power down state, supply current consumption(ICC)isataminimum.Initiatinganyoperation(byactivatingcontrol inputs) will immediately take the device out of the Power Down state. TheIDT72V3683/72V3693/72V36103arecharacterizedforoperationfrom 0 °C to 70°C. Industrial temperature range (-40°C to +85°C) is available by special order. They are fabricated using IDT’s high speed, submicron CMOS technology. |
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