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IDT72V70840 Datasheet(PDF) 12 Page - Integrated Device Technology

Part No. IDT72V70840
Description  3.3 VOLT TIME SLOT INTERCHANGE DIGITAL SWITCH
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

IDT72V70840 Datasheet(HTML) 12 Page - Integrated Device Technology

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COMMERCIALTEMPERATURERANGE
IDT72V70840 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 4,096 x 4,096
JTAG SUPPORT
The IDT72V70840 JTAG interface conforms to the Boundary-Scan stan-
dard IEEE-1149.1. This standard specifies a design-for-testability technique
called Boundary-Scan test (BST). The operation of the boundary-scan
circuitry is controlled by an external test access port (TAP) Controller.
TEST ACCESS PORT (TAP)
The Test Access Port (TAP) provides access to the test functions of the
IDT72V70840. It consists of three input pins and one output pin.
•Test Clock Input (TCK)
TCK provides the clock for the test logic. The TCK does not interfere with
any on-chip clock and thus remain independent. The TCK permits shifting of
test data into or out of the Boundary-Scan register cells concurrently with the
operation of the device and without interfering with the on-chip logic.
•Test Mode Select Input (TMS)
The logic signals received at the TMS input are interpreted by the TAP
Controller to control the test operations. The TMS signals are sampled at the
rising edge of the TCK pulse. This pin is internally pulled to VCC when it is not
driven from an external source.
•Test Data Input (TDI)
Serial input data applied to this port is fed either into the instruction register
or into a test data register, depending on the sequence previously applied to
the TMS input. Both registers are described in a subsequent section. The
received input data is sampled at the rising edge of TCK pulses. This pin is
internally pulled to VCC when it is not driven from an external source.
•Test Data Output (TDO)
Depending on the sequence previously applied to the TMS input, the
contentsofeithertheinstructionregisterordataregisterareseriallyshiftedout
towards the TDO. The data out of the TDO is clocked on the falling edge of the
TCKpulses.Whennodataisshiftedthroughtheboundaryscancells,theTDO
driver is set to a high impedance state.
•Test Reset (
TRST)
Reset the JTAG scan structure. This pin is internally pulled to VCC.
INSTRUCTION REGISTER
In accordance with the IEEE-1149.1 standard, the IDT72V70840 uses
public instructions. The IDT72V70840 JTAG Interface contains a two-bit
instruction register. Instructions are serially loaded into the instruction register
from the TDI when the TAP Controller is in its shifted-IR state. Subsequently,
theinstructionsaredecodedtoachievetwobasicfunctions:toselectthetestdata
registerthatmayoperatewhiletheinstructioniscurrent,andtodefinetheserial
testdataregisterpath,whichisusedtoshiftdatabetweenTDIandTDOduring
data register scanning. See Table below for Instruction decoding.
Value
Instruction
Function
11
Bypass
Select Bypass Register
10
Sample/Preload
Select Boundary Scan Register
01
Sample/Preload
Select Boundary Scan Register
00
EXTEST
Select Boundary Scan Register
TEST DATA REGISTER
As specified in IEEE-1149.1, the IDT72V70840 JTAG Interface contains
two test data registers:
•The Boundary-Scan register
The Boundary-Scan register consists of a series of Boundary-Scan cells
arranged to form a scan path around the boundary of the IDT72V70840 core
logic.
•The Bypass Register
The Bypass register is a single stage shift register that provides a one-bit
path from TDI to its TDO. The IDT72V70840 boundary scan register bits are
showninTable10.Bit0isthefirstbitclockedout.Allthree-stateenablebitsare
active high.
JTAG Instruction Register Decoding


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