Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF Download HTML

IDT72V70840 Datasheet(PDF) 9 Page - Integrated Device Technology

Part No. IDT72V70840
Description  3.3 VOLT TIME SLOT INTERCHANGE DIGITAL SWITCH
Download  21 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

IDT72V70840 Datasheet(HTML) 9 Page - Integrated Device Technology

Back Button IDT72V70840 Datasheet HTML 5Page - Integrated Device Technology IDT72V70840 Datasheet HTML 6Page - Integrated Device Technology IDT72V70840 Datasheet HTML 7Page - Integrated Device Technology IDT72V70840 Datasheet HTML 8Page - Integrated Device Technology IDT72V70840 Datasheet HTML 9Page - Integrated Device Technology IDT72V70840 Datasheet HTML 10Page - Integrated Device Technology IDT72V70840 Datasheet HTML 11Page - Integrated Device Technology IDT72V70840 Datasheet HTML 12Page - Integrated Device Technology IDT72V70840 Datasheet HTML 13Page - Integrated Device Technology Next Button
Zoom Inzoom in Zoom Outzoom out
 9 / 21 page
background image
9
COMMERCIALTEMPERATURERANGE
IDT72V70840 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 4,096 x 4,096
0123
4
5
6
7
8
9
10
11
12
13
14
15
16
ST-BUSFrame
CLK
Offset Value
FE Input
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
GCI Frame
CLK
Offset Value
FE Input
(FD[10:0] = 06H)
(FD11 = 0, sample at CLK LOW phase)
(FD[10:0] = 09H)
(FD11 = 1, sample at CLK HIGH phase)
5715 drw 04
Figure 1. Example for Frame Alignment Measurement
Bit
Name
Description
15-13
Unused
Must be zero for normal operation
12
CFE (Complete
When CFE = 1, the frame evaluation is completed and bits FD10 to FD0 bits contains a valid frame alignment offset. This bit is reset to
Frame Evaluation)
zero, when SFE bit in the CR register is changed from 1 to 0.
11
FD11
The falling edge of FE (or rising edge for GCI mode) is sampled during the CLK-high phase (FD11 = 1) or during the CLK-low phase
(Frame Delay Bit 11) (FD11 = 0). This bit allows the measurement resolution to ½ CLK cycle.
10-0
FD10-0
The binary value expressed in these bits refers to the measured input offset value. These bits are rest to zero when the SFE bit of the
(Frame Delay Bits)
CR register changes from 1 to 0. (FD10 – MSB, FD0 – LSB)
Reset Value:
0000H.
15
14
13
12
11
10
9876543210
0
0
0
CFE
FD11
FD10
FD9
FD8
FD7
FD6
FD5
FD4
FD3
FD2
FD1
FD0
TABLE 7 — .RAME ALIGNMENT REGISTER (.AR) BITS


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21 


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn