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IDT72V70840 Datasheet(PDF) 5 Page - Integrated Device Technology

Part No. IDT72V70840
Description  3.3 VOLT TIME SLOT INTERCHANGE DIGITAL SWITCH
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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IDT72V70840 Datasheet(HTML) 5 Page - Integrated Device Technology

 
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COMMERCIALTEMPERATURERANGE
IDT72V70840 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 4,096 x 4,096
DECRIPTION (CONTINUED)
JTAGTestAccessPort(TAP)andperstreamprogrammableinputoffsetdelay,
variable or constant throughput modes, internal loopback, output enable, and
Processor Mode.
The IDT72V70840 is capable of switching up to 4,096 x 4,096 channels
without blocking. Designed to switch 64 Kbit/s PCM or N x 64 Kbit/s data, the
devicemaintainsframeintegrityindataapplicationsandminimizesthroughput
delay for voice applications on a per channel basis.
The 32 serial input streams (RX) of the IDT72V70840 can be run up to
8.192Mb/sallowing128channelsper125
µsframe.Thedataratesontheoutput
streams (TX) are identical to those on the input stream.
With two main operating modes, Processor Mode and Connection Mode,
the IDT72V70840 can easily switch data from incoming serial streams (Data
Memory) or from the controlling microprocessor (Connection Memory). As
controlandstatusinformationiscriticalindatatransmission,theProcessorMode
isespeciallyusefulwhentherearemultipledevicessharingtheinputandoutput
streams.
With data coming from multiple sources and through different paths, data
enteringthedeviceisoftendelayed. Tohandlethisproblem,theIDT72V70840
has a frame evaluation feature to allow individual streams to be offset from the
frame pulse in half clock-cycle intervals up to +4.5 clock cycles.
The IDT72V70840 also provides a JTAG test access port, an internal
loopback feature, memory block programming, a simple microprocessor
interface and automatic ST-BUS®/GCI sensing to shorten setup time, aid in
debugging and ease use of the device without sacrificing capabilities.
.UNCTIONAL DESCRIPTION
DATA AND CONNECTION MEMORY
All data that comes in through the RX inputs go through a serial-to-parallel
conversion before being stored into internal Data Memory. The 8 KHz frame
pulse (
F0i) is used to mark the 125
µs frame boundaries and to sequentially
address the input channels in Data Memory.
DataoutputontheTXstreamsmaycomefromeithertheSerialInputStreams
(Data Memory) or from the microprocessor (Connection Memory). In the case
thatRXinputdataistobeoutput,theaddressesinconnectionmemoryareused
to specify a stream and channel of the input. The connection memory is setup
in such a way that each location corresponds to an output channel for each
particularstream. Inthatway, morethanonechannelcanoutputthesamedata.
In Processor Mode, the microprocessor writes data to the connection
memorylocationscorrespondingtothestreamandchannelthatistobeoutput.
Thelowerhalf(8leastsignificantbits)oftheconnectionmemoryisoutputevery
frame until the microprocessor changes the data or mode of the channel. By
usingthisProcessorModecapability,themicroprocessorcanaccessinputand
output time-slots on a per channel basis.
The four most significant bits of the connection memory are used to control
per channel functions of the out put streams. Specifically, there are bits for
Processor or Connection mode, Constant or Variable delay, enables or
disables of output drivers, and controls for the Loopback function.
If the per channel OE is set to zero, only that particular channel (8-bits) will
beinthehigh-impedancestate. Ifhowever,theODEinputpinislowortheOutput
Standby Bit (OSB) in the Control Register is low, all of the outputs will be in a
high-impedance state even if a particular channel in connection memory has
enabledtheoutputforthatchannel. Inotherwords,theODEpinandOSBcontrol
bit are master output enables for the device (Table 3).
SERIAL DATA INTERFACE TIMING
The master clock frequency must always be twice the data rate, e.g. for a
serial data rates of 2.048 Mb/s, the master clock (CLK) must be at 4.096 MHz.
The input and output stream data rates will always be identical. See control
register bits DR1-0 description (Table 5) for data and clock rate selections.
TheIDT72V70840providestwodifferentinterfacetimingmodes,ST-BUS®
orGCI.TheIDT72V70840automaticallydetectsthepresenceofaninputframe
pulse and identifies it as either ST-BUS® or GCI. In ST-BUS® format, every
second falling edge of the master clock marks a bit boundary and the data is
clocked in on the rising edge of CLK, three quarters of the way into the bit cell.
In GCI format, every second rising edge of the master clock marks the bit
boundary and data is clocked in on the falling edge of CLK at three quarters
of the way into the bit cell.
INPUT FRAME OFFSET SELECTION
Inputframeoffsetselectionallowsthechannelalignmentofindividualinput
streamstobeoffsetwithrespecttotheoutputstreamchannelalignment(i.e.
F0i).
Although all input data comes in at the same speed, delays can be caused by
variable path serial backplanes and variable path lengths which may be
implemented in large centralized and distributed switching systems. Because
dataisoftendelayedthisfeatureisusefulincompensatingfortheskewbetween
clocks.
Each input stream can have its own delay offset value by programming the
frame input offset registers (FOR, Table 8). The maximum allowable skew is
+4masterclock(CLK)periodsforwardwitharesolutionof1/2clockperiod.The
output frame offset cannot be offset or adjusted.
SERIAL INPUT FRAME ALIGNMENT EVALUATION
The IDT72V70840 provides the frame evaluation (FE) input to determine
different data input delays with respect to the frame pulse
F0i.
A measurement cycle is started by setting the start frame evaluation (SFE)
bitlowforatleastoneframe.WhentheSFEbitintheControlRegisterischanged
from low to high, the evaluation starts. Two frames later, the complete frame
evaluation (CFE) bit of the frame alignment register (FAR) changes from low
to high to signal that a valid offset measurement is ready to be read from bits 0
to 11 of the FAR register. The SFE bit must be set to zero before a new
measurement cycle is started.
In ST-BUS® mode, the falling edge of the frame measurement signal (FE)
isevaluatedagainstthefallingedgeoftheST-BUS® framepulse.InGCImode,
therisingedgeofFEisevaluatedagainsttherisingedgeoftheGCIframepulse.
See Table 7 and Figure 1 for the description of the frame alignment register.
MEMORY BLOCK PROGRAMMING
TheIDT72V70840providesuserswiththecapabilityofinitializingtheentire
connectionmemoryblockintwoframes.Tosetbits12to15ofeveryconnection
memory location, first program the desired pattern in bits 5 to 8 of the Control
Register.
The block programming mode is enabled by setting the memory block
program (MBP) bit of the control register high. When the block programming
enable (BPE) bit of the Control Register is set to high, the block programming
data will be loaded into the bits 12 to 15 of every connection memory location.
The other connection memory bits (bit 0 to bit 11) are loaded with zeros. When
the memory block programming is complete, the device resets the BPE bit to
zero.


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