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IDT72V70840 Datasheet(PDF) 4 Page - Integrated Device Technology

Part No. IDT72V70840
Description  3.3 VOLT TIME SLOT INTERCHANGE DIGITAL SWITCH
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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IDT72V70840 Datasheet(HTML) 4 Page - Integrated Device Technology

 
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COMMERCIALTEMPERATURERANGE
IDT72V70840 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 4,096 x 4,096
PIN DESCRIPTION
SYMBOL
NAME
I/O
DESCRIPTION
GND
Ground.
Ground Rail.
VCC
VCC
+3.3 Volt Power Supply.
TX0-31
TX Output 0 to 31
O
Serial data output stream. These streams may have a data rate of 2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s.
(Three-state Outputs)
RX0-31
RX Input 0 to 31
I
Serial data input stream. These streams may have a data rate of 2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s.
F0i
Frame Pulse
I
This input accepts and automatically identifies frame synchronization signals formatted according to
ST-BUS® and GCI specifications.
FE/HCLK Frame Evaluation/
I
When the WFPS pin is LOW, this pin is the frame measurement input. When the WFPS pin is HIGH, the
HCLK Clock
HCLK (4.096 MHZ clock) is required for frame alignment in the wide frame pulse (WFP) mode.
CLK
Clock
I
Serial clock for shifting data in/out on the serial streams (RX/TX 0-31). This input accepts a 4.096 MHz clock
when data streams @ 2.048 Mb/s, a 8.192 MHz clock when data streams @ 4.096 Mb/s, a 16.384 MHz
clock when data streams @ 8.192 Mb/s.
TMS
Test Mode Select
I
JTAG signal that controls the state transitions of the TAP controller. This pin is pulled HIGH by an internal
pull-up when not driven.
TDI
Test Serial Data In
I
JTAG serial test instructions and data are shifted in on this pin. This pin is pulled HIGH by an internal pull-up
when not driven.
TDO
Test Serial Data Out
O
JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in high-impedance state
when JTAG scan is not enabled.
TCK
Test Clock
I
Provides the clock to the JTAG test logic.
TRST
Test Reset
I
Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-reset state. This pin is
pulled by an internal pull-up when not driven. This pin should be pulsed LOW on power-up, or held LOW,
to ensure that the IDT72V70840 is in the normal functional mode.
RESET
Device Reset
I
This input (active LOW) puts the IDT72V70840 in its reset state that clears the device internal counters,
(Schmitt Trigger Input)
registers and brings TX0-31 and microport data outputs to a high-impedance state. The time constant for a
power up reset circuit must be a minimum of five times the rise time of the power supply. In normal operation,
the
RESET pin must be held LOW for a minimum of 100ns to reset the device.
WFPS
Wide Frame Pulse Select
I
When 1, enables the wide frame pulse (SFP) Frame Alignment interface. When 0, the device operates in
ST-BUS® /GCI mode.
DS
Data Strobe
I
This active LOW input works in conjunction with
CS to enable the read and write operations.
R/
W
Read/Write
I
This input controls the direction of the data bus lines during a microprocessor access.
CS
Chip Select
I
Active LOW input used by a microprocessor to activate the microprocessor port of IDT72V70840.
A0-13
Address Bus 0 to 13
I
These pins allow direct access to Connection Memory, Data Memory and internal control registers.
D0-15
Data Bus 0-15
I/O
These pins are the data bits of the microprocessor port.
DTA
Data Transfer
O
This active LOW signal indicates that a data bus transfer is complete. When the bus cycle ends, this pin
Acknowledgment
drives HIGH and then goes high-impedance, allowing for faster bus cycles with a weaker pull-up resistor. A
pull-up resistor is required to hold a HIGH level when the pin is in high-impedance.
ODE
Output Drive Enable
I
This is the output enable control for the TX0-31 serial outputs. When ODE input is LOW and the OSB bit of
the CR register is LOW, TX0-31 are in a high-impedance state. If this input is HIGH, the TX0-31 output
drivers are enabled. However, each channel may still be put into a high-impedance state by using the per
channel control bit in the connection memory.


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