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IDT72V70840 Datasheet(PDF) 16 Page - Integrated Device Technology

Part No. IDT72V70840
Description  3.3 VOLT TIME SLOT INTERCHANGE DIGITAL SWITCH
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

IDT72V70840 Datasheet(HTML) 16 Page - Integrated Device Technology

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COMMERCIALTEMPERATURERANGE
IDT72V70840 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 4,096 x 4,096
AC ELECTRICAL CHARACTERISTICS - .RAME PULSE AND CLK
Symbol
Parameter
Min.
Typ.
Max.
Units
tFPW(1)
Frame Pulse Width (ST-BUS®, GCI)
Bit rate = 2.048 Mb/s
26
295
ns
Bit rate = 4.096 Mb/s
26
145
ns
Bit rate = 8.192 Mb/s
26
80
ns
tFPS(1)
Frame Pulse Setup time before CLK falling (ST-BUS® or GCI)
5

ns
tFPH(1)
Frame Pulse Hold Time from CLK falling (ST-BUS® or GCI)
10

ns
tCP(1)
CLK Period
Bit rate = 2.048 Mb/s
190
300
ns
Bit rate = 4.096 Mb/s
110
150
ns
Bit rate = 8.192 Mb/s
58
70
ns
tCH(1)
CLK Pulse Width HIGH
Bit rate = 2.048 Mb/s
85
150
ns
Bit rate = 4.096 Mb/s
50
75
ns
Bit rate = 8.192 Mb/s
20
40
ns
tCL(1)
CLK Pulse Width LOW
Bit rate = 2.048 Mb/s
85
150
ns
Bit rate = 4.096 Mb/s
50
75
ns
Bit rate = 8.192 Mb/s
20
40
ns
tr, tf
Clock Rise/Fall Time

10
ns
tHFPW(2)
Wide Frame Pulse Width
Bit rate = 8.192 Mb/s
195
295
ns
tHFPS(2)
Frame Pulse Setup Time before HCLK falling
5
150
ns
tHFPH(2)
Frame Pulse Hold Time from HCLK falling
10
150
ns
tHCP(2)
HCLK (4.096 MHz) Period
Bit rate = 8.192 Mb/s
190
300
ns
tHCH(2)
HCLK (4.096 MHz) Pulse Width HIGH
Bit rate = 8.192 Mb/s
85
150
ns
tHCL(2)
HCLK (4.096 MHz) Pulse Width LOW
Bit rate = 8.192 Mb/s
85
150
ns
tHr,tHf
HCLK Rise/Fall Time

10
ns
tDIF(3)
Delay between falling edge of HCLK and falling edge of CLK
-10
10
ns
NOTES:
1. WFPS Pin = 0.
2. WFPS Pin = 1
3. WFPS Pin = 0 or 1.


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