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PRELIMINARY
CY7C1313BV18
CY7C1911BV18
CY7C1311BV18
CY7C1315BV18
Document Number: 38-05620 Rev. **
Page 2 of 23
Logic Block Diagram (CY7C1311BV18)
CLK
A(18:0)
Gen.
K
K
Control
Logic
Address
Register
D[7:0]
Read Data Reg.
RPS
WPS
Q[7:0]
Control
Logic
Address
Register
Reg.
Reg.
Reg.
16
19
8
32
8
NWS[1:0]
VREF
Write
Reg
16
A(18:0)
19
C
C
Write
Reg
Write
Reg
Write
Reg
8
CQ
CQ
DOFF
Logic Block Diagram (CY7C1911BV18)
CLK
A(18:0)
Gen.
K
K
Control
Logic
Address
Register
D[8:0]
Read Data Reg.
RPS
WPS
Q[8:0]
Control
Logic
Address
Register
Reg.
Reg.
Reg.
18
19
9
36
9
BWS[0]
VREF
Write
Reg
18
A(18:0)
19
C
C
Write
Reg
Write
Reg
Write
Reg
9
CQ
CQ
DOFF
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