8

HM6264A Series

HM6264A Series

Write Timing Waveform (2) (

OE Low Fix)

*6

*5

*7

*8

*9

Address

CS1

CS2

Dout

Din

WE

Valid Data

Notes: 1.

2.

3.

4.

5.

6.

7.

8.

9.

A write occurs during the overlap of a low

CS1, a high CS2, and a low WE. A write begins

at the latest transition among

CS1 going low, CS2 going high and WE going low. A write

ends at the earliest transition among

CS1 going high, CS2 going low and WE going high.

of the write cycle.

During this period, I/O pins are in the output state, therefore the input signals of opposite

phase to the outputs must not be applied.

If

CS1 goes low simultaneously with WE going low or after WE goes low, the outputs

remain in high impedance state.

Dout is the same phase of the latest written data in this write cycle.

Dout is the read data of the next address.

If

CS1 is low and CS2 is high during this period, I/O pins are in the output state. Input signals

of opposite phase to the outputs must not be applied to I/O pins