 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
HFCT-5903E Datasheet(PDF) 3 Page - Agilent(Hewlett-Packard) |
|
||||||||||||||||||||||||||||||
HFCT-5903E Datasheet(HTML) 3 Page - Agilent(Hewlett-Packard) |
|
|
3 / 12 page  3 Functional Description Receiver Section Design The receiver section contains an InGaAs/InP photo detector and a preamplifier mounted in an optical subassembly. This optical subassembly is coupled to a postamp/decision circuit on a separate circuit board. The postamplifier is ac coupled to the preamplifier as illustrated in Figure 1. The coupling capacitor is large enough to pass the FDDI test pattern at 125 MBd and the SONET/SDH test pattern at 155 MBd without significant distortion or performance penalty If a lower signal rate, or a code which has significantly more low frequency content is used, sensitivity, jitter and pulse distortion could be degraded. Figure 1 also shows a filter network which limits the bandwidth of the preamp output signal. The filter is designed to bandlimit the preamp output noise and thus improve the receiver sensitivity. These components will also reduce the sensitivity of the receiver as the signal bit rate is increased above 155 MBd. Noise Immunity The receiver includes internal circuit components to filter power supply noise. Under some conditions of EMI and power supply noise, external power supply filtering may be necessary. If receiver sensitivity is found to be degraded by power supply noise, the filter network illustrated in Figure 3 may be used to improve performance. The values of the filter components are general recommendations and may be changed to suit a particular system environment. Shielded inductors are recommended. Terminating the Outputs The PECL Data outputs of the receiver may be terminated with the standard Thevenin-equivalent 50 ohm to VCC - 2 V termination. Other standard PECL terminating techniques may be used. The two outputs of the receiver should be terminated with identical load circuits to avoid unnecessarily large ac current in VCC. If the outputs are loaded identically the ac current is largely nulled. The SD output of the receiver is PECL logic and must be loaded if it is to be used. The signal detect circuit is much slower that the data path, so the ac noise generated by an asymmetrical load is negligible. Power consumption may be reduced by using a higher than normal load impedance for the SD output. Transmission line effects are not generally a problem as the switching rate is slow. The Signal Detect Circuit The signal detect circuit works by sensing the peak level of the received signal and comparing this level to a reference. Figure 1. Receiver Block Diagram TRANS- IMPEDANCE PRE- AMPLIFIER FILTER GND AMPLIFIER PECL OUTPUT BUFFER PECL OUTPUT BUFFER DATA OUT SIGNAL DETECT CIRCUIT SD DATA OUT |
Similar Part No. - HFCT-5903E |
|
Similar Description - HFCT-5903E |
|
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
