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CY7C1380CV25
CY7C1382CV25
PRELIMINARY
Document #: 38-05240 Rev. *A
Page 7 of 33
TMS
Test Mode Select
Synchronous
This pin controls the Test Access Port state machine. Sampled on the
rising edge of TCK. (BGA Only)
TCK
JTAG serial clock
Serial clock to the JTAG circuit. (BGA Only)
VDD
Power Supply
Power supply inputs to the core of the device. Should be connected to 2.5V
± 5% power supply.
VSS
Ground
Ground for the core of the device. Should be connected to ground of the
system.
VDDQ
I/O Power Supply
Power supply for the I/O circuitry.
VSSQ
I/O Ground
Ground for the I/O circuitry. Should be connected to ground of the system.
NC
-
No Connects.Pins are not internally connected.
36M
72M
144M
-
No Connects. Reserved for address expansion.
Pin Definitions
Name
I/O
Description