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CY7C1380CV25
CY7C1382CV25
PRELIMINARY
Document #: 38-05240 Rev. *A
Page 11 of 33
Notes:
5.
The SRAM always initiates a read cycle when ADSP asserted, regardless of the state of GW, BWE, or BWx. Writes may occur only on subsequent clocks after
the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state. OE is a
“don't care” for the remainder of the write cycle.
6.
OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQ = High-Z when OE is inactive or
when the device is deselected, and DQ = data when OE is active.
Write Cycle Descriptions[1, 5, 6]
Function (1380CV25)
GW
BWE
BWdBWcBWbBWa
Read
1
1
XX
XX
Read
10
11
11
Write Byte 0 – DQa
1
01
11
0
Write Byte 1 – DQb
1
01
10
1
Write Bytes 1, 0
1
01
10
0
Write Byte 2 – DQc
1
01
01
1
Write Bytes 2, 0
1
01
01
0
Write Bytes 2, 1
1
01
00
1
Write Bytes 2, 1, 0
1
0
1
0
0
0
Write Byte 3 – DQd
1
00
11
1
Write Bytes 3, 0
1
00
11
0
Write Bytes 3, 1
1
00
10
1
Write Bytes 3, 1, 0
1
0
0
1
0
0
Write Bytes 3, 2
1
00
01
1
Write Bytes 3, 2, 0
1
0
0
0
1
0
Write Bytes 3, 2, 1
1
0
0
0
0
1
Write All Bytes
1
0
0
0
0
0
Write All Bytes
0
X
X
X
X
X
Function (1382CV25)
GW
BWE
BWbBWa
Read
1
1
X
X
Read
1
0
1
1
Write Byte 0 – DQ[7:0] and DP0
10
1
0
Write Byte 1 – DQ[15:8] and DP1
10
0
1
Write All Bytes
1
0
0
0
Write All Bytes
0
X
X
X
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