VP536E

4

Master Reset

The VP536E can be initialized with the RESET pin. This

is an active low signal and must be active for a minimum of 2

CLK12I clock periods in order for the VP536E to be reset.

CLK12I

HS

VS

RGB/YUV

INPUT DATA

Line 1

Line 2

Line 3

Line 4

Line 17

48 Periods

Field 1

1st

2nd

pixel

pixel

CLK12I

HS

VS

RGB/YUV

INPUT DATA

Line 1

Line 2

Line 3

Line 4

Line 23

58Periods

Field 1

Line 23

1st

2nd

pixel

pixel

Fig. 2a. NTSC Input Timing Diagram

Fig. 2b. PAL Input Timing Diagram

Line 17

NOTE:

1. Coincident falling edges of HS and VS denote the start of an odd field.

3. Input pixel data is ignored during composite blanking periods.

Video Timing Reset

The VP536E also features the ability to independently

reset the video timing generator without affecting the data

path. The TSURST pin controls this function. Taking this pin

high resets the video timing generator. If this pin is left open,

it is internally pulled low.