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M39P0R9070E0 Datasheet(PDF) 2 Page - STMicroelectronics

Part No. M39P0R9070E0
Description  512 Mbit (x16, Multiple Bank, Multi-Level, Burst) Flash Memory 128 Mbit Low Power SDRAM, 1.8V Supply, Multi-Chip Package
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Maker  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
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M39P0R9070E0 Datasheet(HTML) 2 Page - STMicroelectronics

 
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M39P0R9070E0
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Contents
1
Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1
Address inputs (A0-A24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2
LPSDRAM Bank Select Address Inputs (BA0-BA1) . . . . . . . . . . . . . . . . . . . . 9
2.3
Data Inputs/Outputs (DQ0-DQ15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4
Flash Memory Chip Enable Input (EF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.5
Flash Memory Output Enable (GF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.6
Flash Memory Write Enable (WF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.7
Flash Memory Write Protect Input (WPF) . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.8
Flash Memory Reset (RPF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.9
Deep Power-Down (DPDF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.10
Flash Memory Latch Enable (LF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.11
Flash Memory Clock (KF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.12
Flash Memory Wait (WAITF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.13
LPSDRAM Chip Select (ES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.14
LPSDRAM Column Address Strobe (CASS) . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.15
LPSDRAM Row Address Strobe (RASS) . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.16
LPSDRAM Write Enable (WS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.17
LPSDRAM Clock Input (KS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.18
LPSDRAM Clock Enable (KES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.19
LPSDRAM Lower/Upper Data Input/Output Mask (LDQMS/UDQMS) . . . . . 12
2.20
Flash Memory VDDF Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.21
LPSDRAM VDDS Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.22
VDDQ Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.23
Flash Memory VPPF Program Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 13
2.24
VSS Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16


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