Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF Download HTML

IN74LV574 Datasheet(PDF) 1 Page - Integral Corp.

Part No. IN74LV574
Description  Octal D-type flip-flop; positive edge-trigger (3-State)
Download  8 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  INTEGRAL [Integral Corp.]
Direct Link  http://www.iksemi.com/
Logo INTEGRAL - Integral Corp.

IN74LV574 Datasheet(HTML) 1 Page - Integral Corp.

  IN74LV574 Datasheet HTML 1Page - Integral Corp. IN74LV574 Datasheet HTML 2Page - Integral Corp. IN74LV574 Datasheet HTML 3Page - Integral Corp. IN74LV574 Datasheet HTML 4Page - Integral Corp. IN74LV574 Datasheet HTML 5Page - Integral Corp. IN74LV574 Datasheet HTML 6Page - Integral Corp. IN74LV574 Datasheet HTML 7Page - Integral Corp. IN74LV574 Datasheet HTML 8Page - Integral Corp.  
Zoom Inzoom in Zoom Outzoom out
 1 / 8 page
background image
TECHNICAL DATA
1
INTEGRAL
Octal D-type flip-flop;
positive edge-trigger (3-State)
The 74LV574 is a low-voltage Si-gate CMOS device and is pin and
function compatible with 74HC/HCT574.
The 74LV574 is an octal D-type flip–flop featuring separate D-type
inputs for each flip-flop and non-inverting 3-state outputs for oriented
applications. A clock (CP) and an output enable (OE) input are common
to all flip-flops. The eight flip-flops will store the state of their individual
D-inputs that meet the set-up and hold times requirements on the LOW-
to-HIGH CP transition. When OE is LOW, the contents of the eight flip-
flops are available at the outputs. When OE is HIGH, the outputs go to
the high impedance OFF-state. Operation of the OE input does not affect
the state of the flip-flops.
• Output voltage levels are compatible with input levels of CMOS,
NMOS and TTL ICS
• Supply voltage range: 1.0 to 5.5 V
• Low input current: 1.0 µÀ; 0.1 µÀ at Ò = 25 °Ñ
• High Noise Immunity Characteristic of CMOS Devices
IN74LV574
N SUFFIX
PLASTIC DIP
DW SUFFIX
SO
1
20
1
20
ORDERING INFORMATION
IN74LV574N
Plastic DIP
IN74LV574DW
SOIC
IZ74LV574
chip
TA = -40
° to 125° C for all packages
FUNCTION TABLE
Inputs
Output
Output
Enable
Clock
D
Q
L
H
H
L
L
L
L
L,H,
X
no
change
H
X
X
Z
H= high level
L = low level
X = don’t care
Z = high impedance
LOGIC DIAGRAM
PIN 20=VCC
PIN 10 = GND
PIN ASSIGNMENT


Html Pages

1  2  3  4  5  6  7  8 


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn