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IN74LV273 Datasheet(PDF) 1 Page - Integral Corp.

Part No. IN74LV273
Description  Octal D Flip-Flop with Common Clock and Reset
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Maker  INTEGRAL [Integral Corp.]
Homepage  http://www.iksemi.com/
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IN74LV273 Datasheet(HTML) 1 Page - Integral Corp.

   
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TECHNICAL DATA
1
INTEGRAL
Octal D Flip-Flop with Common Clock and Reset
The IN74LV273 is a low-voltage Si-gate CMOS device and is pin and
function compatible with the 74HC/HCT273.
The IN74LV273 has eight edge-triggered, D-type flip-flops with
individual D inputs and Q outputs. The common clock (CP) and master
reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The
state of each D input, one set-up time before the LOW-to-HIGH clock
transition, is transferred to the corresponding output (Qn) of the flip -
flop. All outputs will be forced LOW independently of clock or data
inputs by a LOW voltage level on the MR input. The device is useful for
applications where the true output only is required and the clock and
master reset are common to all storage elements.
• Output voltage levels are compatible with input levels of CMOS,
NMOS and TTL ICS
• Supply voltage range: 1.2 to 5.5 V
• Low input current: 1.0 µÀ; 0.1 µÀ at Ò = 25 °Ñ
• High Noise Immunity Characteristic of CMOS Devices
IN74LV273
N SUFFIX
PLASTIC DIP
DW SUFFIX
SO
1
20
1
20
ORDERING INFORMATION
IN74LV273N
Plastic DIP
IN74LV273DW
SOIC
IZ74LV273
chip
TA = -40
° to 125° C for all packages
LOGIC DIAGRAM
PIN 20=VCC
PIN 10 = GND
FUNCTION TABLE
Inputs
Output
Reset
Clock
D
Q
L
X
X
L
H
H
H
H
L
L
H
L
X
no change
H
X
no change
H= high level
L = low level
X = don’t care
Z = high impedance
PIN ASSIGNMENT
1
2
3
5
4
6
7
8
9
10
V CC
20
18
17
16
15
14
19
11
12
13
GND
RESET
Q0
D0
D1
Q1
Q2
D2
D3
Q3
Q7
D7
D6
Q6
Q5
D5
D4
Q4
CLOCK


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