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IN74LV74D Datasheet(PDF) 7 Page - Integral Corp. |
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IN74LV74D Datasheet(HTML) 7 Page - Integral Corp. |
7 / 7 page IN74LV74 7 INTEGRAL CHIP PAD DIAGRAM Location of marking (mm): left lower corner x=0.520, y=0.865. Chip thickness: 0.46 ± 0.02 mm. PAD LOCATION Location (left lower corner), mm Pad No Symbol X Y Pad size, mm 01 Reset 1 0.118 0.436 0.108 x 0.108 02 Data 1 0.118 0.125 0.108 x 0.108 03 Clock 1 0.286 0.125 0.108 x 0.108 04 Set 1 0.597 0.125 0.108 x 0.108 05 Q 1 0.895 0.125 0.108 x 0.108 06 Q 1 1.100 0.125 0.108 x 0.108 07 GND 1.100 0.423 0.108 x 0.108 08 Q 2 1.100 0.721 0.108 x 0.108 09 Q 2 1.100 0.930 0.108 x 0.108 10 Set 2 0.851 0.949 0.108 x 0.108 11 Clock 2 0.540 0.949 0.108 x 0.108 12 Data 2 0.297 0.949 0.108 x 0.108 13 Reset 2 0.118 0.830 0.108 x 0.108 14 VCC 0.118 0.604 0.108 x 0.108 Note: Pad location is given as per metallization layer 02 01 04 03 06 05 08 07 10 09 12 11 14 13 Chip marking 25LV74 (0,0) X Y 1.32 + 0.03 |
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