TECHNICAL DATA

1

INTEGRAL

3-to-8 line decoder/demultiplexer;

inverting

The IN74LV138 is a low-voltage Si-gate CMOS device and is pin

and function compatible 74HCT138.

The74LV138 accepts three binary weighted address inputs -

• Optimized for Low Voltage applications:1.2 to 3.6 V

• Demultiplexing capability

• Multiple input enabte for easy expansion

• Ideal for memory chip select decoding

• Active LOW mutually exclusive outputs

• Output capability: standard

N SUFFIX

PLASTIC

D SUFFIX

SOIC

1

16

1

16

ORDERING INFORMATION

IN74LV138N Plastic

IN74LV138D SOIC

° to 125° C for all packages

IN74LV138

PIN ASSIGNMENT

LOGIC DIAGRAM

PIN 8 = GND

FUNCTION TABLE

Inputs

Outputs

CS1CS2CS3

A2 A1A0

Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

X X H

X H X

L X X

X X X

X X X

X X X

H H H H H H H H

H H H H H H H H

H H H H H H H H

H L L

H L L

H L L

H L L

L L L

L L H

L H L

L H H

L H H H H H H H

H L H H H H H H

H H L H H H H H

H H H L H H H H

H L L

H L L

H L L

H L L

H L L

H L H

H H L

H H H

H H H H L H H H

H H H H H L H H

H H H H H H L H

H H H H H H H L

H = high level (steady state)

L = low level (steady state)

X = don’t care