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IN74LV74 Datasheet(PDF) 1 Page - Integral Corp.

Part No. IN74LV74
Description  Dual D-type flip-flop with set and reset; positive-edge trigger
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Maker  INTEGRAL [Integral Corp.]
Homepage  http://www.iksemi.com/
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IN74LV74 Datasheet(HTML) 1 Page - Integral Corp.

   
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TECHNICAL DATA
1
INTEGRAL
Dual D-type flip-flop with set and reset;
positive-edge trigger
The IN74LV74 is a low-voltage Si-gate CMOS device and is pin and
function compatible with 74HC/HCT74.
The IN74LV74 is a dual positive edge triggered, D-type flip-flop with
individual data (D) inputs, clock (CP) inputs, set (SD) and (RD) inputs;
also complementary Q and Q outputs.
The set and res et are asynchronous active LOW inputs and operate
independently of the clock input. Information on the data input is
transferred to the Q output on the LOW -to-HIGH transition of the clock
pulse. The D inputs must be stable one set-up time prior to the LOW-to-
HIGH clock transition, for predictable operation. Schmitt-trigger action in
the clock input makes the circuit highly tolerant to slower clock rise and
fall times.
• Output voltage levels are compatible with input levels of CMOS,
NMOS and TTL ICS
• Supply voltage range: 1.2 to 3.6 V
• Low input current: 1.0 µÀ; 0.1 µÀ at Ò = 25 °Ñ
• High Noise Immunity Characteristic of CMOS Devices
IN74LV74
1
14
1
14
N SUFFIX
PLASTIC
D SUFFIX
SOIC
ORDERING INFORMATION
IN74LV74N
Plastic DIP
IN74LV74D
SOIC
IZ74LV74
chip
TA = -40
° to 125° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
PIN 20=VCC
PIN 10 = GND
FUNCTION TABLE
Inputs
Outputs
Set
Reset
Clock
Data
Q
Q
L
H
X
X
H
L
H
L
X
X
L
H
L
L
X
X
H*
H*
H
H
H
H
L
H
H
L
L
H
H
H
L
X
No Change
H
H
H
X
No Change
H
H
X
No Change
*Both outputs will remain high as long as Set and
Reset are low, but the output states are unpredictable
if Set and Reset go high simultaneously.
H= high level
L = low level
X = don’t care
Z = high impedance
1
2
3
5
4
6
7
V CC
14
13
12
11
10
8
9
GND
RESET 1
DATA 1
SET 1
Q1
Q1
RESET 2
DATA2
CLOCK 2
SET 2
Q2
Q2
CLOCK 1


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