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MAX3634 Datasheet(PDF) 3 Page - Maxim Integrated Products

Part No. MAX3634
Description  622Mbps/1244Mbps Burst-Mode Clock Phase Aligner for GPON OLT Applications
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Maker  MAXIM [Maxim Integrated Products]
Homepage  http://www.maxim-ic.com
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MAX3634 Datasheet(HTML) 3 Page - Maxim Integrated Products

   
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622Mbps/1244Mbps Burst-Mode Clock Phase
Aligner for GPON OLT Applications
_______________________________________________________________________________________
3
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.0V to +3.6V, TA = -40
°C to +85°C. Typical values are at VCC = +3.3V, TA = +25°C, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
622Mbps (Notes 1, 2)
500
Serial Data Output Clock-to-Q
Delay (Figure 1)
tCLK-Q
1244Mbps (Notes 1, 2)
250
ps
622Mbps (Notes 1, 2)
500
Serial Data Output Q-to-Clock
Delay (Figure 1)
tQ-CLK
1244Mbps (Notes 1, 2)
250
ps
RATESEL Input High
VIH
2V
RATESEL Input Low
VIL
0.8
V
RATESEL Input Current
VIN = 0V or VCC
-100
+100
µA
Note 1: PECL output must have external termination of 50
Ω to VCC - 2V (Thevenin equivalent).
Note 2: AC parameters are guaranteed by design and characterization.
Note 3: From start of PON burst, 101010101010 preamble sequence.
Note 4: BER, acquisition time requirements are met with 100mVP-P sinusoidal noise on VCC, 0 < fNOISE
≤ 10MHz.
Note 5: Measured with 20psRMS input random jitter (1.244Mbps), 30psRMS (622Mbps)
Note 6: Jitter tolerance refers to the variation in phase between REFCLK and SDI after acquisition.
Typical Operating Characteristics
(VCC = +3.3V and TA = +25
°C, unless otherwise noted)
1.244Gbps
INPUT AND OUTPUT EYE DIAGRAMS
200ps/div
SDI
SDO
622Mbps
INPUT AND OUTPUT EYE DIAGRAMS
400ps/div
SDI
SDO
BURST CAPTURE AT 1.244Gbps
1ns/div
RST
SDI
SDO
LOCK
(SCLK+) - (SCLK-)
(SDO+) - (SDO-)
tCLK-Q
tQ-CLK
Figure 1. Definition of Clock-to-Q and Q-to-Clock Delay


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