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SN54LV165 Datasheet(PDF) 4 Page - Texas Instruments

Part No. SN54LV165
Description  PARALLEL-LOAD 8-BIT SHIFT REGISTERS
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
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SN54LV165 Datasheet(HTML) 4 Page - Texas Instruments

   
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SN54LV165, SN74LV165
PARALLEL-LOAD 8-BIT SHIFT REGISTERS
SCES007B – MARCH 1995 – REVISED APRIL 1996
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
V
SN54LV165
SN74LV165
UNIT
PARAMETER
TEST CONDITIONS
VCC†
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
IOH = – 100 µA
MIN to MAX
VCC – 0.2
VCC – 0.2
VOH
IOH = – 6 mA
3 V
2.4
2.4
V
IOH = – 12 mA
4.5 V
3.6
3.6
IOL = 100 µA
MIN to MAX
0.2
0.2
VOL
IOL = 6 mA
3 V
0.4
0.4
V
IOL = 12 mA
4.5 V
0.55
0.55
II
VI =VCC or GND
3.6 V
±1
±1
µA
II
VI = VCC or GND
5.5 V
±1
±1
µA
ICC
VI =VCC or GND
IO =0
3.6 V
20
20
µA
ICC
VI = VCC or GND,
IO = 0
5.5 V
20
20
µA
nICC
One input at VCC – 0.6 V,
Other inputs at VCC or GND
3 V to 3.6 V
500
500
µA
Ci
VI =VCC or GND
3.3 V
2.5
2.5
pF
Ci
VI = VCC or GND
5 V
3
3
F
† For conditions shown as MIN or MAX, use the appropriate values under recommended operating conditions.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
SN54LV165
VCC = 5.5 V
± 0.5 V
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
fclock
Clock frequency
0
50
0
40
0
30
MHz
t
Pulse duration
CLK high or low
14
18
22
ns
tw
Pulse duration
SH/LD low
14
18
22
ns
SH/LD high before CLK
10
13
17
t
Setup time
SER before CLK
8
11
14
ns
tsu
Setup time
CLK INH before CLK
10
12
15
ns
Data before SH/LD
8
12
17
th
Hold time
SER data after CLK
6
6
5
ns
th
Hold time
Parallel data after SH/LD
6
6
5
ns
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.


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