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554KEXXXXXXBG Datasheet(PDF) 1 Page - Silicon Laboratories |
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554KEXXXXXXBG Datasheet(HTML) 1 Page - Silicon Laboratories |
1 / 20 page Preliminary Rev. 0.31 8/01 Copyright © 2001 by Silicon Laboratories Si5540-DS031 This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Si5540 SiPHY™ OC-192/STM-64 TRANSMITTER Features Complete SONET/SDH transmitter for OC-192/STM-64 data rates with integrated 16:1 multiplexer and DSPLL™ based clock multiplier unit: Applications Description The Si5540 is a fully integrated low-power transmitter for high-speed serial communication systems. It combines high speed clock generation with a 16:1 multiplexer to serialize data for OC-192/STM-64 applications. The Si5540 is based on Silicon Laboratories’ DSPLL ™ technology which eliminates the external loop filter components required by traditional clock multiplier units. In addition, selectable loop filter bandwidths are provided to ensure superior jitter performance while relaxing the jitter requirements on external clock distribution subsystems. Support for data streams up to 10.7 Gbps is also provided for applications that employ forward error correction (FEC). The Si5540 represents a new standard in low jitter, low power and small size for 10 Gbps serial transmitters. It operates from a single 1.8 V supply over the industrial temperature range (–40 °C to 85°C). Functional Block Diagram Data Rates Supported: OC-192/STM-64, 10GbE, and 10.7 Gbps FEC Low Power Operation 0.6 W (typ) Small Footprint: 99-Pin BGA Package (11 x 11 mm) DSPLL™ Based Clock Multiplier Unit w/ selectable loop filter bandwidths OIF SFI-4 Compliant Interface Output Clock Powerdown Operates with 155 or 622 MHz Reference Sources Optional 3.3 V Supply Pin for LVTTL Compatible Outputs Single 1.8 V Supply Operation Sonet/SDH/ATM Routers Add/Drop Multiplexers Digital Cross Connects Optical Transceiver Modules Sonet/SDH Test Equipment TXDO U T TXDIN [15:0] TXCL K16O U T FIF O RST FIFO ER R TXCL K16IN TX M SBSEL TXCL KO UT TXSQ LC H 2 2 2 R EFC LK TXLO L D SPLL TM CM U TXC LKD SBL 2 TXC LK16IN R EFSEL BW SEL 2 32 16 REFRATE Bias R eset Con trol R EXT RES ET ÷ Ordering Information: See page 17. Si5364 Bottom View P RE LI M I NA RY D ATA S H EET |
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