Electronic Components Datasheet Search |
|
554CEXXXXXXBG Datasheet(PDF) 10 Page - Silicon Laboratories |
|
554CEXXXXXXBG Datasheet(HTML) 10 Page - Silicon Laboratories |
10 / 20 page Si 5540 10 Preliminary Rev. 0.31 shift register by an output clock, TXCLK16OUT, that is produced by dividing down the high speed transmit clock, TXCLKOUT, by a factor of 16. The TXCLK16OUT clock output is provided to support 16 bit word transfers between the Si5540 and upstream devices using a counter clocking scheme. The high-speed serial data stream is clocked out of the shift register using TXCLKOUT. Input FIFO The Si5540 integrates a FIFO to decouple data transferred into the FIFO via TXCLK16IN from data transferred into the shift register via TXCLK16OUT. The FIFO is eight parallel words deep and accommodates any static phase delay that may be introduced between TXCLK16OUT and TXCLK16IN in counter clocking schemes. Further, the FIFO will accommodate a phase drift or wander between TXCLK16IN and TXCLK16OUT of up to three parallel data words. The FIFO circuitry indicates an overflow or underflow condition by asserting FIFOERR high. This output can be used to recenter the FIFO read/write pointers by tieing it directly to the FIFORST input. The Si5540 will also recenter the read/write pointers after the device’s power on reset, external reset via RESET, and each time the DSPLL transitions from an out of lock state to a locked state (TXLOL transitions from low to high). Parallel Input To Serial Output Relationship The Si5540 provides the capability to select the order in which data on the parallel input bus is transmitted seri- ally. Data on this bus can be transmitted MSB first or LSB first depending on the setting of TXMSBSEL. If TXMSBSEL is tied low, TXDIN0 is transmitted first fol- lowed in order by TXDIN1 through TXDIN15. If TXMSB- SEL is tied high, TXDIN15 is transmitted first followed in order by TXDIN14 through TXDIN0. This feature simpli- fies board routing when ICs are mounted on both sides of the PCB. Transmit Data Squelch To prevent the transmission of corrupted data into the network, the Si5540 provides a control pin that can be used to force the high speed data output, TXDOUT, to 0. By driving TXSQLCH low TXDOUT will be forced to 0. Reset A device reset can be forced by holding the RESET pin low for at least 1 µs. When RESET is asserted low, the input FIFO pointers reset and the digital control circuitry initializes. When RESET transitions high to start normal operation, the DSPLL will be calibrated. Clock Disable The Si5540 provides a clock disable pin, TXCLKDSBL, that is used to disable the high-speed serial data clock output, TXCLKOUT. When the TXCLKDSBL pin is asserted, the positive and negative terminals of CLK- OUT are tied to 1.5 V through 50 Ω on-chip resistors. This feature is used to reduce power consumption in applications that do not use the high speed transmit data clock. Bias Generation Circuitry The Si5540 makes use of an external resistor to set internal bias currents. The external resistor allows pre- cise generation of bias currents which significantly reduces power consumption versus traditional imple- mentations that use an internal resistor. The bias gener- ation circuitry requires a 3.09 k Ω (1%) resistor connected between REXT and GND. |
Similar Part No. - 554CEXXXXXXBG |
|
Similar Description - 554CEXXXXXXBG |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |