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554KAXXXXXXBG Datasheet(PDF) 9 Page - Silicon Laboratories |
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554KAXXXXXXBG Datasheet(HTML) 9 Page - Silicon Laboratories |
9 / 20 page S i5540 Preliminary Rev. 0.31 9 Functional Description The Si5540 is a fully integrated, low power, SONET/ SDH transmitter for OC-192/STM-64 applications. It combines a high performance clock multiplier unit (CMU) with a 16:1 serializer that has a low-speed interface compliant with the Optical Interface Forum (OIF) SFI-4 standard. The CMU uses a phase-locked loop (PLL) architecture based on Silicon Laboratories’ proprietary DSPLL™ technology. This technology is used to generate ultra- low jitter clock and data outputs that provide significant margin to the SONET/SDH specifications. The DSPLL architecture also utilizes a digitally implemented loop filter that eliminates the need for external loop filter components. As a result, sensitive noise coupling nodes that typically cause degraded jitter performance in crowded PCB environments are removed. The DSPLL also reduces the complexity and performance requirements of reference clock distribution strategies for OC-192/STM-64 optical port cards. This is possible because the DSPLL provides selectable wideband and narrowband loop filter settings that allow the user to set the jitter attenuation characteristics of the CMU to accommodate reference clock sources that have a high jitter content. Unlike traditional analog PLL implementations, the loop filter bandwidth is controlled by a digital filter inside the DSPLL and can be changed without any modification to external components. DSPLL™ Clock Multiplier Unit The Si5540’s clock multiplier unit (CMU) uses Silicon Laboratories’ proprietary DSPLL technology to generate a low jitter, high frequency clock source capable of producing a high speed serial clock and data output with significant margin to the SONET/SDH specifications. This is achieved by using a digital signal processing (DSP) algorithm to replace the loop filter commonly found in analog PLL designs. This algorithm processes the phase detector error term and generates a digital control value to adjust the frequency of the voltage controlled oscillator (VCO). Because external loop filter components are not required, sensitive noise entry points are eliminated, thus making the DSPLL less susceptible to board-level noise sources. Therefore, SONET/SDH jitter compliance is easier to attain in the application. Programmable Loop Filter Bandwidth The digital loop filter in the Si5530 provides two bandwidth settings that support either wideband or narrowband jitter transfer characteristics. The filter bandwidth is selected via the BWSEL control input. In traditional PLL implementations, changing the loop filter bandwidth would require changing the values of external loop filter components. In narrowband mode, a loop filter cutoff of 12 kHz is provided. This setting makes the Si5540 more tolerant of jitter on the reference clock source. As a result, the complexity of the clock distribution circuitry used to generate the physical layer reference clocks can be simplified without compromising jitter margin to the SONET/SDH specification. In wideband mode, the loop filter provides a cutoff of 50 kHz. This setting is desirable in applications where the reference clock is provided by a low jitter source like the Si5364 Clock Synchronization IC or Si5320 Precision Clock Multiplier/Jitter Attenuator IC. This allows the DSPLL to more closely track the precision reference source resulting in the best possible jitter performance. Reference Clock The CMU within the Si5530 is designed to operate with reference clock sources that are either 1/16th or 1/64th the desired output data rate. The CMU will support operation with data rates between 9.9 Gbps and 10.7 Gbps and the reference clock should be scaled accordingly. For example, to support 10.66 Gbps operation the reference clock source would be approximately 167 MHz or 666 MHz. The REFRATE input pin is used to configure the device for operation with one of the two supported reference clock submultiples of the data rate. The Si5540 supports operation with two selectable reference clock sources. The first configuration uses an externally provided reference clock that is input via REFCLK. The second configuration uses the parallel data clock, TXCLK16IN, as the reference clock source. When using TXCLK16IN as the reference source, the narrowband loop filter setting may be preferable to remove jitter that may be present on the data clock. The selection of reference clock configuration is controlled via the REFSEL input. The Si5540 will drive the TXLOL output high to indicate the DSPLL has locked to the selected reference source. Serialization The Si5540 includes serialization circuitry that combines a FIFO with a parallel to serial shift register. Low speed data on the parallel input bus, TXDIN[15:0], is latched into the FIFO on the rising edge of TXCLK16IN. The data in the FIFO is clocked into the |
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