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XRT75L03 Datasheet(PDF) 5 Page - Exar Corporation |
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XRT75L03 Datasheet(HTML) 5 Page - Exar Corporation |
5 / 92 page ![]() XRT75L03 THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR REV. 1.0.4 II 4.3.2 Interfacing to the line: ....................................................................................................................... 43 4.4 TRANSMIT DRIVE MONITOR: ............................................................................................................................. 44 4.5 TRANSMITTER SECTION ON/OFF: ...................................................................................................................... 44 5.0 The Receiver Section: ...................................................................................................................... 44 5.1 AGC/EQUALIZER: ............................................................................................................................................ 44 Figure 16. Transmit Driver Monitor set-up. ..................................................................................................... 44 5.1.1 Interference Tolerance: ..................................................................................................................... 45 Figure 17. Interference Margin Test Set up for DS3/STS-1 ........................................................................... 45 5.2 CLOCK AND DATA RECOVERY: ......................................................................................................................... 46 Figure 18. Interference Margin Test Set up for E3. ........................................................................................ 46 TABLE 9: INTERFERENCE MARGIN TEST RESULTS .............................................................................................. 46 5.3 B3ZS/HDB3 DECODER: .................................................................................................................................. 47 5.4 LOS (LOSS OF SIGNAL) DETECTOR: ................................................................................................................ 47 5.4.1 DS3/STS-1 LOS Condition: ................................................................................................................ 47 DISABLING ALOS/DLOS DETECTION: ......................................................................................................... 47 5.4.2 E3 LOS Condition: ............................................................................................................................. 47 TABLE 10: THE ALOS (ANALOG LOS) DECLARATION AND CLEARANCE THRESHOLDS FOR A GIVEN SETTING OF LOSTHR AND REQEN (DS3 AND STS-1 APPLICATIONS) ................................................................... 47 Figure 19. Loss Of Signal Definition for E3 as per ITU-T G.775 .................................................................... 48 Figure 20. Loss of Signal Definition for E3 as per ITU-T G.775. .................................................................... 48 5.4.3 Muting the Recovered Data with LOS condition: ............................................................................ 49 6.0 Jitter: ................................................................................................................................................. 49 6.1 JITTER TOLERANCE - RECEIVER: ...................................................................................................................... 49 6.1.1 DS3/STS-1 Jitter Tolerance Requirements: ..................................................................................... 49 Figure 21. Jitter Tolerance Measurements ..................................................................................................... 49 6.1.2 E3 Jitter Tolerance Requirements: ................................................................................................... 50 Figure 22. Input Jitter Tolerance For DS3/STS-1 .......................................................................................... 50 Figure 23. Input Jitter Tolerance for E3 ......................................................................................................... 50 6.2 JITTER TRANSFER - RECEIVER/TRANSMITTER: .................................................................................................. 51 6.3 JITTER ATTENUATOR: ...................................................................................................................................... 51 TABLE 11: JITTER AMPLITUDE VERSUS MODULATION FREQUENCY (JITTER TOLERANCE) ..................................... 51 TABLE 12: JITTER TRANSFER SPECIFICATION/REFERENCES ............................................................................... 51 6.3.1 Jitter Generation: ............................................................................................................................... 52 7.0 Serial Host interface: ....................................................................................................................... 52 TABLE 13: JITTER TRANSFER PASS MASKS ....................................................................................................... 52 Figure 24. Jitter Transfer Requirements and Jitter Attenuator Performance .................................................. 52 TABLE 14: FUNCTIONS OF SHARED PINS ............................................................................................................ 53 TABLE 15: XRT75L03 REGISTER MAP - QUICK LOOK ........................................................................................ 54 ................................................................................................................................................................. 56 THE REGISTER MAP AND DESCRIPTION FOR THE XRT75L03 3-CHANNEL DS3/E3/STS-1 LIU IC 56 Legend: .................................................................................................................................................................. 56 TABLE 16: COMMAND REGISTER ADDRESS MAP, WITHIN THE XRT75L03 3-CHANNEL DS3/E3/STS-1 LIU W/ JITTER ATTENUATOR IC ................................................................................................................................. 56 THE GLOBAL/CHIP-LEVEL REGISTERS ............................................................................................... 58 ................................................................................................................................................................. 58 REGISTER DESCRIPTION - GLOBAL REGISTERS .............................................................................. 58 TABLE 17: LIST AND ADDRESS LOCATIONS OF GLOBAL REGISTERS .................................................................... 58 TABLE 18: APS/REDUNDANCY CONTROL REGISTER - CR0 (ADDRESS LOCATION = 0X00) .................................. 58 TABLE 19: BLOCK LEVEL INTERRUPT ENABLE REGISTER - CR32 (ADDRESS LOCATION = 0X20) ......................... 61 TABLE 20: BLOCK LEVEL INTERRUPT STATUS REGISTER - CR33 (ADDRESS LOCATION = 0X21) ......................... 62 TABLE 21: DEVICE/PART NUMBER REGISTER - CR62 (ADDRESS LOCATION = 0X3E) .......................................... 63 ................................................................................................................................................................. 64 THE PER-CHANNEL REGISTERS ......................................................................................................... 64 TABLE 22: CHIP REVISION NUMBER REGISTER - CR63 (ADDRESS LOCATION = 0X3F) ........................................ 64 TABLE 23: COMMAND REGISTER ADDRESS MAP, WITHIN THE XRT75L03 3-CHANNEL DS3/E3/STS-1 LIU W/ JITTER ATTENUATOR IC ................................................................................................................................. 64 REGISTER DESCRIPTION - PER CHANNEL REGISTERS ................................................................... 66 |