XRT75L03 datasheet(49/92 Pages) EXAR

Part #	XRT75L03

Description	THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR

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Manufacturer	EXAR [Exar Corporation]

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XRT75L03

THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR

REV. 1.0.4

46

5.2

Clock and Data Recovery:

The Clock and Data Recovery Circuit extracts the embedded clock, RxClk_n from the sliced digital data stream

and provides the retimed data to the B3ZS (HDB3) decoder.

The Clock Recovery PLL can be in one of the following two modes:

TRAINING MODE:

In the absence of input signals at RTIP_n and RRing_n pins, or when the frequency difference between the

recovered line clock signal and the reference clock applied on the ExClk_n input pins exceed 0.5%, a Loss of

Lock condition is declared by toggling RLOL_n output pin “High” (in Hardware Mode) or setting the RLOL_n bit

to “1” in the control registers (in Host Mode). Also, the clock output on the RxClk_n pins are the same as the

reference clock channel.

FIGURE 18. INTERFERENCE MARGIN TEST SET UP FOR E3.

TABLE 9: INTERFERENCE MARGIN TEST RESULTS

MODE

CABLE LENGTH (ATTENUATION)INTERFERENCE TOLERANCE

E3

0 dB

Equalizer “IN”

-17 dB

12 dB

-14 dB

DS3

0 feet

-15 dB

225 feet

-15 dB

450 feet

-14 dB

STS-1

0 feet

-15 dB

225 feet

-14 dB

450 feet

-14 dB

Attenuator 1

N

S

Sine Wave

Generator

17.184mHz

Signal Source

223-1 PRBS

Attenuator 2

∑

Test

Equipment

DUT

(XRT75L03)

Cable Simulator

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XRT75L03 Datasheet(PDF) 49 Page - Exar Corporation

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