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A42MX09-2TQ100M Datasheet(PDF) 61 Page - List of Unclassifed Manufacturers

Part # A42MX09-2TQ100M
Description  40MX and 42MX FPGA Families
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Manufacturer  ETC1 [List of Unclassifed Manufacturers]
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A42MX09-2TQ100M Datasheet(HTML) 61 Page - List of Unclassifed Manufacturers

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40MX and 42MX FPGA Families
v6.0
1-55
CMOS Output Module Timing5
tDLH
Data-to-Pad HIGH
3.4
3.8
5.5
6.4
9.0
ns
tDHL
Data-to-Pad LOW
4.1
4.5
4.2
5.0
7.0
ns
tENZH
Enable Pad Z to HIGH
3.7
4.1
4.6
5.5
7.6
ns
tENZL
Enable Pad Z to LOW
4.1
4.5
5.1
6.1
8.5
ns
tENHZ
Enable Pad HIGH to Z
6.9
7.6
8.6
10.2
14.2
ns
tENLZ
Enable Pad LOW to Z
7.5
8.3
9.4
11.1
15.5
ns
tGLH
G-to-Pad HIGH
5.8
6.5
7.3
8.6
12.0
ns
tGHL
G-to-Pad LOW
5.8
6.5
7.3
8.6
12.0
ns
tLSU
I/O Latch Set-Up
0.7
0.8
0.9
1.0
1.4
ns
tLH
I/O Latch Hold
0.0
0.0
0.0
0.0
0.0
ns
tLCO
I/O Latch Clock-to-Out (Pad-to-
Pad), 64 Clock Loading
8.7
9.7
10.9
12.9
18.0
ns
tACO
Array Clock-to-Out (Pad-to-Pad),
64 Clock Loading
12.2
13.5
15.4
18.1
25.3
ns
dTLH
Capacity Loading, LOW to HIGH
0.04
0.04
0.05
0.06
0.08
ns/pF
dTHL
Capacity Loading, HIGH to LOW
0.05
0.05
0.06
0.07
0.10
ns/pF
Table 33 •
A42MX09 Timing Characteristics (Nominal 3.3V Operation) (Continued)
(Worst-Case Commercial Conditions, VCCA = 3.0V, TJ = 70°C)
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Units
Parameter Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.


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