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40MX and 42MX FPGA Families
v6.0
1-37
Input Module Predicted Routing Delays1
tIRD1
FO=1 Routing Delay
2.1
2.4
2.2
3.2
4.5
ns
tIRD2
FO=2 Routing Delay
2.6
3.0
3.4
4.0
5.6
ns
tIRD3
FO=3 Routing Delay
3.1
3.6
4.1
4.8
6.7
ns
tIRD4
FO=4 Routing Delay
3.6
4.2
4.8
5.6
7.8
ns
tIRD8
FO=8 Routing Delay
5.7
6.6
7.5
8.8
12.4
ns
Global Clock Network
tCKH
Input Low to HIGH
FO = 16
FO = 128
4.6
4.6
5.3
5.3
6.0
6.0
7.0
7.0
9.8
9.8
ns
tCKL
Input High to LOW
FO = 16
FO = 128
4.8
4.8
5.6
5.6
6.3
6.3
7.4
7.4
10.4
10.4
ns
tPWH
Minimum Pulse
Width HIGH
FO = 16
FO = 128
2.2
2.4
2.6
2.7
2.9
3.1
3.4
3.6
4.8
5.1
ns
tPWL
Minimum Pulse
Width LOW
FO = 16
FO = 128
2.2
2.4
2.6
2.7
2.9
3.01
3.4
3.6
4.8
5.1
ns
tCKSW
Maximum Skew
FO = 16
FO = 128
0.4
0.5
0.5
0.6
0.5
0.7
0.6
0.8
0.8
1.2
ns
tP
Minimum Period
FO = 16
FO = 128
4.7
4.8
5.4
5.6
6.1
6.3
7.2
7.5
10.0
10.4
ns
fMAX
Maximum
Frequency
FO = 16
FO = 128
188
181
175
168
160
154
139
134
83
80
MHz
Table 28 •
A40MX02 Timing Characteristics (Nominal 5.0V Operation) (Continued)
(Worst-Case Commercial Conditions, VCC = 4.75V, TJ = 70°C)
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Units
Parameter Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Notes:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool from the Designer software to check the hold
time for this macro.
4. Delays based on 35pF loading.
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