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554KAXXXXXXBGR Datasheet(PDF) 7 Page - Silicon Laboratories |
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554KAXXXXXXBGR Datasheet(HTML) 7 Page - Silicon Laboratories |
7 / 20 page S i5540 Preliminary Rev. 0.31 7 Table 3. AC Characteristics (TXCLK16OUT, TXCLK16IN, TXCLKOUT, TXDIN, TXDOUT) (VDD = 1.8 V ±5%, TA = –40°C to 85°C) Parameter Symbol Test Condition Min Typ Max Unit TXCLKOUT Frequency fclkout — 9.95 10.7 GHz TXCLKOUT Duty Cycle tch/tcp, Figure 2 45 — 55 % Output Rise Time (TXCLKOUT, TXDOUT) tR Figure 3 — 25 — ps Output Fall Time (TXCLKOUT, TXDOUT) tF Figure 3 — 25 — ps TXCLKOUT Setup to TXDOUT tsu Figure 2 25 — — ps TXCLKOUT Hold From TXDOUT thd Figure 2 25 — — ps Output Return Loss 400 kHz–10 GHz 10 GHz–16 GHz TBD TBD — — — — dB dB TXCLK16OUT Frequency fCLKIN Figure 2 — 622 667 MHz TXCLK16OUT Duty Cycle tch/tcp, Figure 2 40 — 60 % TXCLK16OUT Rise & Fall Times tR, tF 100 — 300 ps TXDIN Setup to TXCLK16IN tDSIN — — 300 ps TXDIN Hold from TXCLK16IN tDHIN — — 300 ps TXCLK16IN Frequency fCLKIN — 622 667 MHz TXCLK16IN Duty Cycle tch/tcp, Figure 2 40 — 60 % TXCLK16IN Rise & Fall Times tR, tF 100 — 300 ps Table 4. AC Characteristics (Clock Multiplier Characteristics) (VDD = 1.8 V ±5%, TA = –40°C to 85°C) Parameter Symbol Test Condition Min Typ Max Unit Jitter Generation—Deterministic JDET(PP) PRBS-23 — 0.020 TBD UIPP Jitter Generation—Random JGEN(RMS) —0.005 TBD UIRMS Jitter Transfer Bandwidth JBW BWSEL = 0 — — 12 kHz BWSEL = 1 — — 50 kHz Jitter Transfer Peaking — 0.05 0.1 dB Acquisition Time TAQ Valid REFCLK — 15 20 ms Input Reference Clock Frequency RCFREQ REFRATE = 1 — 622 667 MHz REFRATE = 0 — 155 167 MHz Input Reference Clock Duty Cycle RCDUTY 40 — 60 % Input Reference Clock Frequency Tolerance RCTOL –100 — 100 ppm Note: Bellcore specifications: GR-1377-CORE, Issue 5, December 1998. |
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