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SN74LS175 Datasheet(PDF) 4 Page - ON Semiconductor |
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SN74LS175 Datasheet(HTML) 4 Page - ON Semiconductor |
4 / 8 page SN74LS175 http://onsemi.com 4 AC CHARACTERISTICS (TA = 25°C) Limits Symbol Parameter Min Typ Max Unit Test Conditions fMAX Maximum Input Clock Frequency 30 40 MHz tPLH tPHL Propagation Delay, MR to Output 20 20 30 30 ns VCC = 5.0 V CL = 15 pF tPLH tPHL Propagation Delay, Clock to Output 13 16 25 25 ns CL 15 F AC SETUP REQUIREMENTS (TA = 25°C) Limits Symbol Parameter Min Typ Max Unit Test Conditions tW Clock or MR Pulse Width 20 ns ts Data Setup Time 20 ns VCC =5 0V th Data Hold Time 5.0 ns VCC = 5.0 V trec Recovery Time 25 ns AC WAVEFORMS Figure 1. Clock to Output Delays, Clock Pulse Width, Frequency, Setup and Hold Times Data to Clock Figure 2. Master Reset to Output Delay, Master Reset Pulse Width, and Master Reset Recovery Time 1.3 V 1.3 V 1.3 V Q Q tPLH tPLH tPHL 1.3 V *The shaded areas indicate when the input is permitted to *change for predictable output performance. 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V 1/fmax tw ts(H) th(H) ts(L) th(L) CP tPHL tPLH tW tPHL CP trec Q MR D Q * 1.3 V 1.3 V DEFINITIONS OF TERMS SETUP TIME (ts) — is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from LOW to HIGH in order to be recognized and transferred to the outputs. HOLD TIME (th) — is defined as the minimum time following the clock transition from LOW to HIGH that the logic level must be maintained at the input in order to ensure continued recognition. A negative HOLD TIME indicates that the correct logic level may be released prior to the clock transition from LOW to HIGH and still be recognized. RECOVERY TIME (trec) — is defined as the minimum time required between the end of the reset pulse and the clock transition from LOW to HIGH in order to recognize and transfer HIGH Data to the Q outputs. |
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